|
|
发表于 2009-5-17 07:18:12
|
显示全部楼层
Install RF design kit in Cadence
Cadence RF Design Methodology Kit
Adopt the latest verification technologies for an optimized and repeatable RF design processTheRF Design Methodology Kit delivers verified methodologies packaged in asystem-to-tapeout RFIC design flow, demonstrated on a segmentrepresentative design.
Cadence RF Design Methodology Kit Datasheet »
TheCadence® RF Design Methodology Kit shortens product development cycletime by increasing RF design productivity and silicon predictability.It demonstrates advanced methodologies for intelligently managing RLCKparasitics, inductor synthesis and modeling, full-chip verificationthrough a "local" envelope technique, and PLL simulation. The Kit alsolinks system-level design with IC implementation, helping designersquickly and accurately verify complete designs that includesystem-level digital, analog baseband, and RF circuitry.
TheRF Design Methodology Kit is based on an 802.11b/g CMOS WLAN referencedesign, which uses IP from Helic S.A. Athens, Greece. The segmentrepresentative design focuses on simplifying challenges associated withthe RF transceiver and analog portion of the baseband circuitry. Fullyextracted RLCK views ensure silicon predictability by accuratelyverifying the chip at the circuit level and upper levels with detailedparasitic information. Intelligent RC reduction and simulationstrategies further ensure rapid simulation results. Reusable,pre–set-up testbenches, models, and simulation plans allow RF designersto fully and quickly leverage the silicon-accurate design capabilitiesof Virtuoso® custom design technologies.
Kit benefits- Increases silicon predictability and eliminates re-spins
- Verifies wireless IC designs within a system-level context
- Delivers a full-chip functional verification methodology
- Develops and validates functional verification models with embedded assertions
- Simultaneously verifies RF, analog, digital, and system domains
- Effectively uses and manages parasitic data
- Analyzes noise distribution and quickly prototypes noise isolation schemes
- Offers seamless top-down and bottom-up design processes
- Speeds RF design turnaround time
- Provides a prescribed advanced methodology demonstrated on a reference design
- Accurately models and characterizes PLL at the transistor level
- Accelerates top-level simulation using a perturbation projection vector (PPV) method
- Reuses testbenches, simulation plans, and models from the reference design
- Rapidly implements and models inductors early in the process via inductor synthesis
- Intelligently manages RLCK extracted views for fast, accurate chip-level simulation
Kit contents- 802.11 b/g CMOS WLAN reference design from Helic, including RX, TX, and AMS blocks at the behavioral level
- Complete 802.11 b/g testbenches at both the block and chip level
- Complete behavioral models, transistor-level schematics, and layout for the reference design
- Detailed step-by-step documentation and hands-on workshops to help users to validate the overall flow
- Proven and validated RFIC and system IC methodologies
- Pin-accurate behavioral and silicon-accurate calibrated models
- Reusable, pre-setup components including testbenches, models, and simulation plans for all RF transceiver blocks
- Noise modeling for system-level simulation
- Applicability consulting designed to map the verified and demonstrated methodologies to a specific customer design
|
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2009-5-2 10:48:38
