【急招】北京VIA急招1~3年工作经验engineer

doudouha

基本信息及要求
1.所有职位均需要硕士及以上学历1-3年的工作经验
2.需要4月底之前到岗

职位信息
职位1： Logic Design Engineer
【Responsibilities】
1. Logic design development/methodology/maintenance.
2. Design related specifications/documents
3. System debugging
【Requirements】
1. Master degree in microelectronic, computer science or related, 1-3 years experience in IC design;
2. Expertise in logic design, verification, synthesis, STA, Familiar with ASIC design flow and popular EDA tools;
3. Programming skills in verilog or VHDL; Familiar with any script language (such as unix shell, tcl, perl etc);
4. Knowledge of PC architecture and bus specifications(PCI/DDR/PCIE…) is a plus;
5. Strong problem solving skills, team working spirit;
6. Good speaking and writing skills in English

职位2：Hardware System Design Engineer
【Responsibilities】
1. In charge of FPGA emulation platform layout design and debug;
2. In charge of reference board/ silicon debug board layout design;
3. In charge of IC components management and sourcing;
4. In charge of boards’ management.
【Requirements】
1. MS in electronic, computer science or related;
2. Knowledge of Circuit, board design, PCB layout and Signal Integrity, especially high-speed layout experience(up to 5Gbps signals);
3. Knowledge of general ICs for board design;
4. Familiar with FPGA/ARM system;
5. Familiar with High speed board design / RF board design is a plus;
6. CET6, Proficiency in reading English materials.

职位3：DFT Engineer
【Responsibilities】
1.DFT;
2.High speed testing;
3.Logic Design;
4.Test program development.
【Requirements】
1.MS or PHD of E.E, Microelectronics or Computer Science;
2.Knowledge or courses (taken) of Logic design, Microelectronics Circuit, Basic Electromagnetism are required;
3.Knowledge on Fault/Test Synthesis, ATPG and BIST algorithms are desired;
4.Hands-on IC test development (ATE) or IC Verilog simulation experience is highly desired;
5.Language requirement: Mandarin / English.

职位4：Physical Design Engineer
【Responsibilities】
1. ASIC backend design project execution.
2. ASIC backend design flow/methodology development/maintenance.
3. EDA tool evaluation.
4. Internal script development/maintenance, utilizing Perl, TCL and C-Shell.
【Requirements】
1. Master degree in Electrical Engineering, or related engineering fields,3-5 years experience in P&R.
2. Strong verbal communication and interpersonal skills to work closely with a variety of individual contributors and managers; Team work spirit
3. Good spoken and written English skills.
4. The following items are plus:
a) Experienced in commercial EDA tools (e.g., Synopsys, Cadence, Mentor, Magma etc)

有意者请尽快将个人简历发送至carol.ha@usense.com.cn
谢谢~~~~~~