Basically these two simulators (NC-Verilog and Verilog-XL) are very different in terms of architecture and engine itself.
NC-Verilog is compiled-code generator and Verilog-XL is an interpreter. All the Verilog modules compiled by NC-Verilog are objects by which the engine elaborate and simulate.
NC-Verilog and NC-VHDL can read in Verilog and VHDL design, respectively. They can used in Pre-Sim (after the design is synthesizied to netlist) and Post-Sim (netlist after place and route), as long as the netlist is either in Verilog or VHDL.