|
|
发表于 2009-6-23 00:30:05
|
显示全部楼层
LX5280Features- High-performance 32-bit RISC-DSP core
- Superscalar, dual-issue 32-bit embedded processor function, with dual Multiply Accumulate (MAC)
- Operates at 200 MHz in a 0.18 um ASIC process and 33 MHz in a EP20K1000Eor larger device
- Supports MIPSI instruction set architecture [size=-1](see note 1 below)
- Supports MIPS16 code compression
- Includes an optional dual-MAC engine
- Includes optional EJTAG on-chip software debug functionality
- Supported by industry standard development tools and real-time operatingsystems
General DescriptionThe LX5280 is a 32-bit reduced instruction set computer (RISC) digitalsignal processing (DSP) processorwhich executes the MIPS-I instruction set [size=-1](see note 1 below)with the RADIAXDSP extensions. It allowsdesigners to take advantage of a wide array of software developmenttoolsavailable from commercial suppliers to develop code for a high-speed,high-performance DSP function. Multiplication, division, and RADIAXoperations areperformed in hardware by a dual-MAC engine.
Like Lexra's other products, the LX5280 can be configured to execute MIPS16compressed code, and on-chip code debug can be performed on the LX5280 withthe configurable EJTAG block.
The combination of a 32-bit RISC and high-performance DSP architecture in asingle processor function eliminates the need for a separate DSP andmicrocontroller in many applications. This architecture simplifies development andreduces system-on-chip size, cost, and power consumption.
Architecture Overview
The LX5280 megafunction is based on Lexra's high-performance LX-5280embedded processor architecture. The following are characteristics ofthe LX5280 CPU:
- The LX5280 incorporates an eight-port register file. Four 32-bit source operands can be supplied and four destinations updated per cycle.
- Instructions are executed by two parallel six-stage pipelines. The pipelines are designed so that all internal transactions and interfaces occur on the positive edge of the processor clock. Two-phase clocks are not used.
- The LX5280 extends the standard MIPS-I exception handling model. There are eight additional hardware prioritized interrupts, each with a dedicated interrupt vector. This improves real-time interrupt response.
- The LX5280 runs all code written for the Lexra LX4180, but up to 35% faster
The LX5280 can be configured with the following optional features:
- The Lexra Bus Controller (LBC) connects peripheral functions and secondary memories to the processor's own local buses. It is a non-multiplexed, non-pipelined, and a non-parity-checked bus that provides the easiest protocol for design integration. On the processor side, the easiest protocol provides a four word deep write buffer and control for byte and half-word transfers. On the peripheral side, the LBC is designed to interface easily with industry standard bus protocols, such as peripheral component interconnect (PCI), universal serial bus (USB) and IEEE Std. 1394.
- MIPS16 instruction compression reduces program size by up to forty percent. On-chip programs require less memory, resulting in cost saving for system-on-chip designs.
- The LX5280 implements the industry standard EJTAG 2.0.0 specification for full-speed debug with real-time instruction trace.
- The LX5280 is supported by development tools from Green Hills Software Inc., Wind River Systems, and Embedded Performance Inc.
|
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
