研发讨论：除法器的设计

haichao

I wanted to use a 32/16 divider circuit in one of my designs. I found
Synopsys designware provides Pipelined dividers and decided to use it.
I synthesised DW-divider and found a 3-stage pipeline required to meet
my timing requirement of 20MHz(50ns) in TSMC .13u technology.
Since I wanted to FPGA prototyping for my asic, I thought of using Core
generator divider while synthesising for Xilnx FPGA..
Now the Interesting fact I found is, a 32/16 divider from Xlinx core
genrator can be synthesised(using XST synthesis)to 150Mhz easily for a
Virtex-2 (Xc2v2000)FPGA with just one stage pipeline..
At the same time DC-ultra 2004.06-1 is struggling with Designware
foundation divider for meeting a timing of 20MHz with 3 stage
pipeline....
I am confused.......... I always thought ASIC synthesis gives more
frequency for an RTL code...
What I can assume is SYNOPSYS Designware divider is a very bad
implementation of divider...
Any comments/Clues are welcome..

Thanks
Deepu John
--------------------
I would imagine that the Xilinx core takes multiple cycles to perform
the divide (and thus is not pipelined), whereas with the Synopsys
divider, you can probably start one divide per cycle, each having a
latency of 3 cycles. Don't know though, never used them.
Cheers,
Jon
--------------------
Did you use the &quotipelined divider" with a setting of 1 result every
clock? Every 8 clocks? I saw two versions of Pilelined Divider for the
Core Generator when I did a quick search on the Xilinx website. There
should be full data sheets there for referencing details.
FPGAs do a decent job with carry chains. Since that structure is used
often enough, it's pretty decent in speed. A test I ran a while back
for my own implementation suggested I could get a 16/16 divider running
with about 80 ns in one clock cycle without any constraints in a
Spartan-2E device if I recall correctly. A faster speed grade Virtex-2
may perform much better.
You *are* dividing by a variable, not a constant, right?

-------------------------
1. I don't believe it can run 150MH without pipelines within the FPGA.
2. There are some hardcore of multipliers in the FPGA and it is used to
do divide by multiplications.
3. Please post futher information about it.
4. For pipeline divide algorithm, every clock may permit to feed data
with several clocks of delays to get the result.
Weng
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zipl1985

看不懂

mmic1978

有些道理，需仔细想想~~

jieting612

see see

tonywanghui

let me see

tt

Thanks for sharing ideal from the master

cat-floating

这些原创的讨论有价值

chaoivy1

写过软件设计的人写硬件除法的时候不会实现了啊

kharthik

Anybody know thw solution to DC Ultra