Verilog-A from SmartSpice Training

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mscyc0909

What Is SmartSpice Verilog-A?
- The SmartSpice Verilog-A is a high-level Analog Hardware Description Language (AHDL) that uses modules as the basic component to describe the structure and behavior of analog systems and their components
- With the analog statements of VERILOG-A, you can describe a wide range of conservative systems and signal-flow systems; such as electrical, mechanical, fluid dynamic, and thermodynamic systems
- To simulate systems that contain VERILOG-A components, you must have a VERILOG-A license and the SmartSpice simulator installed on your system
- To describe a system, specify both the structure of the system and the behavior of its components
- In VERILOG-A with the SmartSpice circuit simulator, the structures are defined at different levels
- At the highest level, you can define the overall system structure in a netlist
- At the lower, more specific levels, you can define the internal structure of modules by defining the interconnections among submodules

mscyc0909

- Training program-5
- 19 pages

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