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新的一篇,谢谢!
“ESD protection design in TSMC 0.35-μm CMOS cell library,” Ming-Dou Ker, H.-H. Chang, C.-C. Wang, and H.-R. Yeng
Proc. of 1998 International Conference on Computer Systems Technology for Industrial Applications--Chip Technology, Taiwan, Apr. 8-10, 1998, pp. 63-67.
还有一篇,谢谢!
“Design strategy on electrostatic discharge (ESD) protection for nano-scale CMOS integrated circuits (invited paper),”
Ming-Dou Ker
Proc. of 2004 Taiwan International Conference on Nano Science and Technology (TICON), Hsinchu, Taiwan, Jun. 30-Jul. 3, 2004, pp. 132-137.
寻求IEEE ESD论文,谢谢!谢谢!谢谢!谢谢!谢谢!谢谢!
K.-H. Oh, C. Duvvury, K. Banerjee, and W. Dutton, “Impact of
gate-to-contact spacing on ESD performance of salicided deep submicron
nMOS transistors,” IEEE Trans. Electron Devices, vol. 49, pp.
2183–2192, Dec. 2002.
T.-Y. Chen, M.-D. Ker, and C.-Y. Wu, “Experimental investigation on
the HBM ESD characteristics of CMOS devices in a 0.35-m silicided
process,” in Proc. Int. Symp. VLSI Technology, Systems, and Applications,
1999, pp. 35–38.
谢谢!谢谢!谢谢!谢谢!谢谢!谢谢!
[ 本帖最后由 semico_ljj 于 2009-1-16 21:02 编辑 ] |
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