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Digital VLSI Design with Verilog(book)
This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project.
In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basicsto everything necessary for synthesis of an entire 70,000 transistor,full-duplex serializer - deserializer, including synthesizable PLLs.
Digital VLSI Design With Verilog is all an engineer needs for in-depthunderstanding of the verilog language: Syntax, synthesis semantics, simulation,and test. Complete solutions for the 27 labs are provided on theaccompanying CD-ROM. For a reader with access to appropriate electronicdesign tools, all solutions can be developed, simulated, andsynthesized as described in the book.
A partial list of design topics includes design partitioning, hierarchydecomposition, safe coding styles, back-annotation, wrapper modules,concurrency, race conditions, assertion-based verification, clocksynchronization, and design for test.
Coverage of specific devices includes basic discussion and exerciseson flip-flops, latches, combinational logic, muxes, counters,shift-registers, decoders, state machines, memories (including parityand ECC), FIFOs, and PLLs. Verilog specify blocks, with their path delays and timing checks, also are covered |
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