/* PCI based addresses */
#define PCI_MEM_ADRS 0x50000000
#define PCI_MEM_SIZE 0x01000000 /*16MB */
#define PCI_MEM_SIZE_MASK PCI_SIZE_MASK_16M /* This should match PCI_MEM_SIZE */
#define PCI_MEMIO_ADRS 0x60000000
#define PCI_MEMIO_SIZE 0x01000000 /*16MB */
#define PCI_MEMIO_SIZE_MASK PCI_SIZE_MASK_16M /* This should match PCI_MEMIO_SIZE */
#define PCI_IO_ADRS 0x70000000
#define PCI_IO_SIZE 0x00100000 /* IO Space is not available */
/* CPU from PCI bus */
#define PCI_MSTR_MEM_BUS 0x00000000
#define PCI_MSTR_MEM_SIZE PCI_LOCAL_MEM_SIZE
#define PCI_BRIDGE_PIMMR_BASE_ADRS 0x40000000
/* CPU Address that is visible from PCI */
#define PCI_LOCAL_MEM_BUS LOCAL_MEM_LOCAL_ADRS
#define PCI_LOCAL_MEM_SIZE LOCAL_MEM_SIZE
/* This should match LOCAL_MEM_SIZE - if not statically defined buffers
need to be used for PCI devices */
#define PCI_MSTR_MEM_SIZE_MASK PCI_SIZE_MASK_64M
#ifndef PCI_CFG_TYPE
# ifdef INCLUDE_PCI_AUTOCONF
# define PCI_CFG_TYPE PCI_CFG_AUTO
# else
# define PCI_CFG_TYPE PCI_CFG_FORCE
# endif /* INCLUDE_PCI_AUTOCONF */
#endif /* PCI_CFG_TYPE */
#endif /* INCLUDE_PCI */