[第一帖]Power Distribution Network Design Methodologies .Istvan Novak

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Chapter 9: Distributed Matched Bypassing for Board-Level Power Distribution Networks
Istvan Novak, Senior Staff Engineer, Sun Microsystems
Leesa Noujeim, Staff Engineer, Sun Microsystems
Valerie St. Cyr, Supply Base Development Manager, Sun Microsystems
Nick Biunno, Principal Engineer, Sanmina-SCI
Atul Patel, Process Engineer, Sanmina-SCI
George Korony, Senior Member of Technical Staff, AVX Corp.
Andy Ritter, Senior Member of Technical Staff, AVX Corp.
9.1: Abstract
9.2: Introduction
9.3: Distributed Matched Bypassing of Power Distribution Networks
9.4: Implementation of Distributed Matched Bypassing
9.5: The Concept of the Bypass Resistor
9.6: Conclusion

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Chapter 10: Comparison of Power Distribution Network Design Methods: An Approach to System-Level Power Distribution Analysis
Dale Becker, Senior Technical Staff Member, IBM Corp.
10.1: Abstract
10.2: Introduction
10.3: A Computer System
10.4: Power Distribution Noise Analysis
10.5: Summary

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Chapter 11: Bypass Filter Design Considerations for Modern Digital Systems, a Comparative Evaluation of the Big 'V,' Multipole, and Many Pole Bypass Strategies
Steve Weir, Consultant, Teraspeed Consultant Group
11.1: Abstract
11.2: What Does the Bypass Network Do?
11.3: Multilayer Chip Capacitor Bypass Basics
11.4: Bypass Strategies--Three Methods, Three Faiths?
11.5: Summary
11.6: Conclusion

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Chapter 12: Comparison of Power Distribution Network Design Methods: Bypass Capacitator Selection Based on Time Domain and Frequency Domain Preferences
Istvan Novak, Senior Signal Integrity Staff Engineer, Sun Microsystems
12.1: Abstract
12.2: Introduction
12.3: So, What Is the Metric?
12.4: Comparison of Popular Methods Based on Lumped Self-Impedance
12.5: Component Placement
12.6: Implementation Examples
12.7: Conclusion

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Chapter 13: PDN Design Strategies: Ceramic SMT Decoupling Capacitators--What Values Should I Choose
James L. Knighten, Senior Staff Engineer, NCR Corp.
Bruce Archambeault, Distinguished Engineer, IBM
Jun Fan, Senior Hardware Engineer, NCR Corp.
Giuseppe Selli, Ph.D. Candidate, University of Missouri-Rolla
Samuel Connor, Senior Engineer, IBM
James L. Drewniak, Professor, University of Missouri-Rolla
13.1: Introduction
13.2: The Power Bus Function
13.3: The Decoupling Capacitor
13.4: Interconnect Inductance
13.5: Conclusion

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Chapter 14: Power Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events
Ralf Schmitt, Signal Integrity Engineer, Rambus, Inc.
Joong-Ho Kim, Signal Integrity Engineer, Rambus, Inc.
Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
June Feng, Signal Integrity Engineer, Rambus, Inc.
Woopoung Kim, Signal Integrity Engineer, Rambus, Inc.
Dan Oh, Signal Integrity Engineer, Rambus, Inc.
14.1: Abstract
14.2: Introduction
14.3: Supply Noise Modeling Methodology for Interface Systems
14.4: SSN Model for DDR2 Test System
14.5: Determining Worst-Case Switching Profiles
14.6: Correlating Supply Noise Parameters
14.7: Measuring Supply Noise on Internal Supply Voltage
14.8: Summary

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Chapter 15: Analysis of Supply Noise Induced Jitter in Gigabit I/O Interfaces
Ralf Schmitt, Signal Integrity Engineers, Rambus, Inc.
Hai Lan, Signal Integrity Engineer, Rambus, Inc.
Chris Madden, Signal Integrity Engineer, Rambus, Inc.
Chuck Yuan, Signal Integrity Engineer, Rambus, Inc.
15.1: Abstract
15.2: Introduction
15.3: Power Supply Design Environment Requirements for Gigabit I/O Interfaces
15.4: Overview of Gigabit I/O Interface Test System
15.5: Measurement of Supply Noiseâ

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Chapter 16: PCB Design Methods for Optimum FPGA SerDes Jitter Performance
Steve Weir, Consultant, Teraspeed Consulting Group
Steve McMorrow, President, Teraspeed Consulting Group
Al Neves, Consultant, Teraspeed Consulting Group
Tom Dagostino, Vice President, Teraspeed Consulting Group
Brian Vicich, Signal Integrity Engineer, Samtec, Inc.
16.1: Abstract
16.2: FPGA SerDes Design Challenge
16.3: Virtex 4TM Rocket I/O Transmitter
16.4: MGT PDN PCB Reference Model
16.5: Linear Regulator Ripple Regulator
16.6: Jitter Evaluation Test Vehicle
16.7: Jitter Evaluation Tests
16.8: Summary
16.9: Conclusion

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Chapter 17: Power Distribution System Design
Mark Alexander, Senior Staff Engineer, Xilinx, Inc.
17.1: Abstract
17.2: Required PCB Decoupling Capacitors
17.3: Basic Decoupling Network Principles
17.4: Role of Inductance
17.5: Simulation Methods
17.6: PDS Measurements
17.7: Optical Decoupling Network Design
17.8: Other Concerns and Causes

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Chapter 18: Aperiodic Resonant Excitation of Microprocessor Power Distribution Systems and the Reverse Pulse Technique
Victor Drabkin, Senior Member of Technical Staff, Hewlett-Packard
Chris Houghton, Senior Member of Technical Staff, Hewlett-Packard
Isaac Kantorovich, Senior Member of Technical Staff, Hewlett-Packard
Michael Tsuk, Senior Member of Technical Staff, Hewlett-Packard
18.1: Abstract
18.2: Introduction
18.3: Definitions
18.4: Reverse Pulse Technique--Plausible Reasoning
18.5: Reverse Pulse Techniques--Proof
18.6: Development
18.7: Conclusion