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2008年6月美国亚特兰大射频集成电路会议上的workshop！
Workshop Abstract: The nanometer CMOS processes bring devices with high fT, enabling the SoC integration
of multi-GHz RF communication systems. This gave a tremendous cost, area and power saving when compared with traditional bipolar or BiCMOS solutions. However, the higher noise, larger mismatches and wider process variations of nanometer FETs require extensive digital calibration to compete with traditional analog solutions. This workshop addresses advanced analog-digital co-design techniques which trade the higher speed and larger digital gate density of nanometer CMOS processes for relaxed analog front-end specifications. First, the ways to correct the nanometer CMOS device impairments and the very low-voltage circuit design challenges are presented. Then, new mixed-signal and all-digital approaches to implement traditional analog functions are investigated. Final presentations show how the analog-digital co-design techniques are applied to the major wireless applications: cellular, WLAN and broadcast.
Topics：
WSG-01
Correctting Nanometer CMOS RF Circuit Impairments, B. Nauta, University of Twente, Enschede, Netherlands
WSG-02
Circuit Design Techniques for Ultra-low Voltage RF Receivers, P. R. Kinget, Columbia University, New York, United States
WSG-03
Digital Signal Processing Techniques for Linearity and Efficiency Enhancement of Envelope Tracking, EER, and Doherty Amplifiers, L. E. Larson, P. A. Asbeck, D. S. Kimball, UCSD, LaJolla, United States
WSG-04
Designing CMOS wireless system-on-a-chip, D. Su1, M. Zargari2, 1Atheros Communcations, Santa Clara, United States, 2Atheros Communications, Irvine, United States
WSG-05
Digital Assisted RF Modems, A. Hanke, Infineon, Neubiberg, Germany
WSG-06
Analog-assisted digital and digitally-assisted analog electronics for RF-SoC transceiver front-ends, J. R. Long, TU Delft, Delft, Netherlands |
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发表于 2008-9-1 22:24:36
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