2008.07 IEEE JSSC

s2618017

1.A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

2.A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications

s2618017

3.A CMOS 5 nV$/surd $Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN

4.A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

s2618017

5.A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

6.An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

s2618017

5.A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

6.An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

s2618017

7. A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors

8.Light Source Position Measurement Technique Applicable in SOI Technology

9. Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes

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10.Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop
11.Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range
12.A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay

s2618017

13.An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage

14.A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold

15.40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW

16.A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD

s2618017

17.A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion

18.A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver

19.Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability

20.Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

basildy

ponderboy

good,thanks!