关于CPPLL的simulink建模问题

disgustingman1

本人最近在进行CPPLL的simulink建模学习，首先根据PM和环路带宽使用MATLAB脚本确定了LPF的参数；随后进行simulink建模；鄙人比较迷惑的一点是：最终PLL的锁定后，Vctrl有一个周期性的纹波；想请教一下这个问题可能的原因。
本人在积分器后接的sin函数获得具有相位信息的信号，发现它是周期性的有一段幅值变化异常，因此在经过sign函数后出现了一段波形的“缺失”，这应该是导致周期性长时间CP充电LPF导致的原因。但是不知道应该如何去解决该问题，还希望大佬们赐教。

carl11223344

Reference spur due to PFD+Charge-pump cascading, featuring periodic (Tref) comparison between VCO feedback signal(with divider) and reference clock even though two periodic signals are phase-locked !
This phenomenon is mainly due to the mechanism of tri-state phase-frequency detector nature - generating UP/DN control signals to switch charge-pump though there is theoretically "zero phase error". Aforementioned fact causes charge-pump injects zero net-charge to loop-filter, so do not affect the phase acquisition function of PLL. However the switching actions of charging/discharging current sources will perturb the control voltage line and modulate VCO, degrading spectrum purity in terms of spurious tone relative to harmonics of reference frequency.