Prime Time User Guide 中英对照 第五章（下）

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Example 1: Setting a Maximum Transition Limit

To set a maximum transition limit of 2.0 units on the ports of OUT*, enter

pt_shell> set_max_transition 2.0 [get_ports "OUT*"]

To set the default maximum transition limit of 5.0 units on the current design, enter

pt_shell> set_max_transition 5.0 [current_design]

To set the maximum transition limit of 4.0 units on all pins in the CLK1 clock domain, for rising transitions in data paths only, enter

pt_shell> set_max_transition 4.0 [get_clocks CLK1] -data_path -rise

Example 2: Scaling the Maximum Transition by Slew Threshold

Consider library lib1 having a slew threshold of 10/90. The design has a maximum transition limit set by you at 0.3 ns. The main library slew threshold for rise and fall is 30/70. By using the report_constraint -max_transition -all_violators -significant_digits 4 command, you get:

考虑库 lib1 的转换阈值为 10/90。该设计的最大转换限值由您设置，为 0.3 ns。上升和下降的main library slew threshold为 30/70。通过使用 report_constraint -max_transition -all_violators -significant_digits 4 命令，您可以获得：

Example 3: Scaling the Maximum Transition by Derating

Consider library lib1 having a slew derating factor of 0.5 and a slew threshold for rise and fall of 30/70. You set a maximum transition on the design at 0.3 ns. The main library slew threshold for rise and fall is 30/70 and slew derate is 1.0. By using the report_constraint -max_transition -all_violators -significant_digits 4 command, you see:

考虑库 lib1 的slew derating系数为 0.5，rise and fall的slew threshold为 30/70。将design的最大转换设置为 0.3 ns。 rise and fall的 main library slew threshold为 30/70， slew derate为 1.0。通过使用 report_constraint -max_transition -all_violators -significant_digits 4 命令，您可以看到：

Minimum Capacitance

To specify a minimum capacitance limit on specific ports or on the entire design, run the set_min_capacitance command. Setting a capacitance limit on a port applies to the net connected to that port. Setting a capacitance limit on a design sets the default capacitance limit for all nets in the design.

要指定特定端口或整个design的最小电容限制，请执行 set_min_capacitance 命令。在端口上设置电容限制适用于连接到该端口的网络。在设计上设置电容限值会为设计中的所有网络设置默认电容限值。

The set_min_capacitance command applies the min_capacitance attribute (a design rule constraint) on the specified objects. Capacitance constraint checks are only applicable for output pins. During a constraint check, the most restrictive constraint is considered.

set_min_capacitance命令对指定对象应用 min_capacitance 属性（设计规则约束）。电容约束检查仅适用于输出引脚。在约束检查期间，将考虑限制性最强的约束。

To see the capacitance constraint evaluations, run the report_constraint -min_capacitance command. To see port capacitance limits, run the report_port -design_rule command. To see the default capacitance settings for the current design, run the report_design command. To remove user-specified capacitance limits, run the remove_min_capacitance command.

要看电容约束的评估，请运行 report_constraint -min_capacitance 命令。要查看端口电容的限制，请运行 report_port -design_rule 命令。要查看当前设计的默认电容设置，请运行 report_design 命令。要删除用户指定的电容限制，请运行 remove_min_capacitance 命令。

To set a minimum capacitance limit of 0.2 units on the ports of OUT*, enter

pt_shell> set_min_capacitance 0.2 [get_ports "OUT*"]

To set the default minimum capacitance limit of 0.1 units on the current design, enter

pt_shell> set_min_capacitance 0.1 [current_design]

Maximum Capacitance

To specify a maximum capacitance limit, run the set_max_capacitance command. Setting a capacitance limit on a port applies to the net connected to that port. Setting a capacitance limit on a design sets the default capacitance limit for all nets in the design. You have the option to additionally specify a maximum capacitance limit on pins or clocks. When specified on clocks, the pins in the clock domain are constrained. Within a clock domain, you can optionally restrict the constraint further to only clock paths or data paths and only to rising or falling capacitance.

要指定最大电容，请运行 set_max_capacitance 命令。在端口上设置电容限制适用于连接到该端口的net。在design上设置电容限制会为design中的所有net设置默认电容限制。可以选择额外指定pin或clock的最大电容限制。当在clock上指定时，此时钟域中的pin会受到约束。在时钟域中，您可以选择性地将约束进一步限制为仅clock path或data path，仅限制在上升或下降电容上。

The set_max_capacitance command applies the max_capacitance attribute (a design rule constraint) on the specified objects. Capacitance constraint checks are only applicable for output pins. During a constraint check, the most restrictive constraint is considered.

set_max_capacitance 命令将 max_capacitance 属性 （设计规则约束） 应用于指定的对象。电容约束检查仅适用于 output pins。在约束检查期间，将考虑限制性最严的约束。

To apply a global derating factor to max_capacitance values, set the timing_max_capacitance_derate variable.

要将 global derating factor应用于max_capacitance值，请设置 timing_max_capacitance_derate 变量。

To see the capacitance constraint evaluations, run the report_constraint -max_capacitance command.

To see port capacitance limits, run the report_port -design_rule command. To see the default capacitance settings for the current design, run the report_design command. To remove user-specified capacitance limits, run the remove_max_capacitance command.

要查看电容约束值，请运行 report_constraint -max_capacitance 命令。

要查看端口电容限制，请运行 report_port -design_rule 命令。要查看当前设计的默认电容设置，请运行 report_design 命令。要删除用户指定的电容限制，请运行 remove_max_capacitance 命令。

Constraining Rise and Fall Maximum Capacitance

To constrain rise and fall maximum capacitance at the output of the driver pins in the clock path and data path for clocks in the design, use the set_max_capacitance command.

要限制 design中 clock 在 clock path 和 data path 中 driver pins 的output 的上升和下降最大电容，请使用 set_max_capacitance 命令。

The tool applies maximum capacitance constraints on a clock to all pins in the clock network (clock path) and the pins in the launching path of the clock (data path of the clock). Optionally, you can restrict constraints on a clock to a clock path, data path, rise, and fall capacitance.

该工具将 clock 上的最大电容约束应用于 clock network （clock path） 中的所有 pins 和 clock 的 launch path （data path of the clock）中的 pins。或者，您可以将 clock 的约束限制在 clock path、data path、rise 和 fall capacitance上。

If the list of objects is a clock list, you can optionally restrict the constraint to only certain path types or transition types by using the -clock_path, -data_path, -rise, or -fall options.

如果对象列表是 clock list，则可以选择使用 -clock_path、-data_path、-rise 或 -fall 选项将约束限制为仅某些 path types 或 transition types。

If a pin (port) is subject to different maximum capacitance constraints specified on the design, library, clock (and port), the most restrictive constraint has priority. The tool reports the slack at a pin as the difference between the most restrictive constraint and the total capacitance at the pin (port).

如果 pin(port) 受 design、library、clock （和 port） 上指定的不同 maximum capacitance constraints 的约束，则最严格的 constraint 具有优先权。该工具将最严格的约束与 pin(port)上的总电容之间的差值报告为 pin 处的slack。

This feature is applicable to generated clocks. To report the constraint violations, use the report_constraint command.

此功能适用于 generated clocks。要报告约束冲突，请使用 report_constraint 命令。

Frequency-Based Maximum Capacitance Checks

A library can contain lookup tables that specify frequency-based max_capacitance values for each driver pin. The pin frequency is the maximum frequency of all clocks that launch signals arriving at the pin.

库可以包含查找表，这些表为每个 driver pin指定基于频率的 max_capacitance 值。pin frequency 是所有 clocks 发射到达 pin 的信号的最大频率。

By default, the tool considers the max_capacitance values from frequency-based lookup tables if available. Design rule constraint (DRC) checking for attribute reporting, the report_constraint command, extracted timing model (ETM) generation, and ECO fixing use the smallest of the following max_capacitance values:

默认情况下，该工具会考虑基于频率的查找表中的max_capacitance值（如果可用）。用于属性报告的设计规则约束 （DRC） 检查、report_constraint 命令、提取时序模型 （ETM） 的生成和 ECO 修复使用以下max_capacitance值中的最小值：

• The max_capacitance value from the lookup table in the library

• The library-cell max_capacitance value

• All user-specified max_capacitance values defined at the pin, port, clock, and design levels

To completely ignore any max_capacitance values from the lookup table, set the timing_enable_library_max_cap_lookup_table variable to false.

要完全忽略查找表中的任何max_capacitance值，请将timing_enable_library_max_cap_lookup_table 变量设置为 false。

To give precedence to the max_capacitance value from the lookup table over the library-cell max_capacitance value, set the timing_library_max_cap_from_lookup_table variable to true.

要使查找表中的 max_capacitance 值优先于 library-cell max_capacitance值，请将timing_library_max_cap_from_lookup_table 变量设置为 true。

The following table shows how the variable settings affect the selection of the max_capacitance values.

下表显示了变量设置如何影响 max_capacitance 值的选择。

Maximum Capacitance Checking With Case Analysis

By default, maximum capacitance checking is not performed on pins in the path of constant propagation. To enable maximum capacitance checking on the constant propagation path, set the timing_enable_max_capacitance_set_case_analysis variable to true.

默认情况下，不会对 constant propagation path 中的 pins 执行最大 capacitance 检查。要在恒定传播路径上启用最大电容检查，请将 timing_enable_max_capacitance_set_case_analysis 变量设置为 true。

Maximum Fanout Load

The set_max_fanout command sets a maximum fanout load for specified output ports or designs. This command sets the max_fanout attribute (a design rule constraint) on the specified objects.

set_max_fanout 命令为指定的 output ports 或 designs 设置最大 fanout load 。此命令在指定对象上设置 max_fanout 属性 （设计规则约束）。

Setting a maximum fanout load on a port applies to the net connected to that port. Setting a maximum fanout load on a design sets the default maximum for all nets in the design. In case of conflict between these two values, the more restrictive value applies.

在port上设置maximum fanout适用于连接到该port的net。在design上设置maximum funout会设置design中所有net的默认最大值。如果这两个值之间存在冲突，则应用限制性更强的值。

Library cell pins can have a max_fanout value specified. PrimeTime uses the more restrictive of the limit you set or the limit specified in the library.

Library cell pins 可以指定 max_fanout 值。PrimeTime 使用您设置的limit或库中指定的limit中限制性更强的limit。

To see maximum fanout constraint evaluations, use the report_constraint -max_fanout command. To see port maximum fanout limits, use the report_port -design_rule command. To see the default maximum fanout setting for the current design, use the report_design command.

要查看maximum funout约束评估，请使用 report_constraint -max_fanout 命令。要查看port 的maximum funout限制，请使用 report_port -design_rule 命令。要查看当前design的默认maximum funout设置，请使用 report_design 命令。

To undo maximum fanout limits you set on ports or designs, use the remove_max_fanout command.

要撤消在port或design上设置的最大扇出限制，请使用 remove_max_fanout 命令。

To set a maximum fanout limit of 2.0 units on the ports IN*, enter the following syntax：

pt_shell> set_max_fanout 2.0 [get_ports "IN*"]

To set the default maximum fanout limit of 5.0 units on the current design, enter the following syntax:

pt_shell> set_max_fanout 5.0 [current_design]

Fanout Load Values for Output Ports

The fanout load for a net is the sum of fanout_load attributes for the input pins and output ports connected to the net. Output pins can have maximum fanout limits, specified in the library or set through the set_max_fanout command. By default, ports are considered to have a fanout load of 0.0. The set_fanout_load command specifies the expected fanout load for output ports in the current design.

net的 fanout load 是连接到net的 input pins 和 output ports 的 fanout_load 属性之和。输出pin可以设置max funout limit，在库中指定或通过 set_max_fanout 命令设置。默认情况下，port的funout load为 0.0。set_fanout_load 命令指定当前 design中 output ports 的预期 fanout load 。

To set the fanout load on ports matching OUT* to 3.0, enter the following syntax:

pt_shell> set_fanout_load 3.0 "OUT*"

For more information, see the Synopsys Timing Constraints and Optimization User Guide.

Ideal Networks

PrimeTime allows you to create ideal networks, on which no design rule constraints are checked. During the pre-layout design stages, you might prefer to ignore large unoptimized networks with high fanout and capacitance, and focus instead on violations arising from other sources. Using ideal networks reduces runtime because PrimeTime uses “ideal timing” rather than internally calculated timing. In this way, ideal networks are similar to ideal clock networks, but they can also be applied to data networks.

PrimeTime 允许您创建ideal networks，无需检查设计规则约束。在布局前设计阶段，您可能更愿意忽略具有高扇出和大电容的未优化networks，而专注于其他source引起的违例。使用dieal networks可以减少运行时间，因为 PrimeTime 使用“ideal timing”而不是内部计算的timing。通过这种方式，ideal networks类似于理想的 clock network，但它们也可以应用于data network。

Ideal networks — sets of connected ports, pins, nets, and cells — are exempt from timing updates and design rule constraint fixing. That is, ideal networks ignore max_capacitance, max_fanout, and max_transition design rule checks. When you specify the source of the ideal network, the pins, ports, nets, and cells contained therein are treated as ideal objects. You or ideal propagation must mark ideal objects.

Ideal nwtwork—— 连接的 ports、pins、nets 和 cells 的集合 — 不受 timing updates 和 design rule constraint fixing的约束。也就是说，ideal network会忽略 max_capacitance、max_fanout 和 max_transition 设计规则检查。当您指定ideal network的源时，其中包含的 pins、ports、nets 和 cells 都将被视为理想对象。你或理想传播必须标记理想对象。

To learn more about ideal networks, see

• Propagating Ideal Network Properties

• Using Ideal Networks

• Using Ideal Latency

• Using Ideal Transition

• Reporting of Ideal Clocks in Full Clock Expanded Mode

Propagating Ideal Network Properties

When you specify the source objects (ports, leaf-level pins) of an ideal network, the nets, cells, and pins in the transitive fanout of the source objects can be treated as ideal.

当您指定ideal network的源对象 （ports， leaf-level pins） 时，源对象的可传播扇出中的net、cell、pin可以被视为理想。

Propagation of the ideal network property is governed by the following rules:

Ideal network属性的传播受以下规则控制：

• Pin is marked as ideal if it is one of the following:

◦ Pin is specified in the object list of the set_ideal_network command

◦ Driver pin and its cell are ideal

◦ Load pin attached to an ideal net

• Net is marked as ideal if all its driving pins are ideal.

• Combinational cell is marked as ideal if either all input pins are ideal or it is attached to a constant net and all other input pins are ideal.

Note:

Ideal network propagation can traverse combinational cells, but it stops at sequential cells.

PrimeTime propagates the ideal network during a timing update and propagates again from ideal source objects as necessary to account for changes in the design, for example, ECOs.

Ideal network传播可以遍历组合单元，但它会停止在时序单元处。

PrimeTime 在 timing update 期间传播理想网络，并根据需要从理想 source objects 再次传播，以考虑 design（例如 ECOs）中的更改。

Using Ideal Networks

Using the set_ideal_network command, specify which networks you want set as ideal. Indicate the sources of the ideal network with the object_list argument. For example, the following command sets the ideal network property on the input port P1, which is propagated along the nets, cells, and pins in the transitive fanout of P1:

使用 set_ideal_network 命令，指定要设为理想的networks。使用 object_list 参数指示理想networks的source。例如，以下命令在输入端口 P1 上设置ideal network属性，该属性沿 P1 的传递扇出的net、cell和pin传播：

pt_shell> set_ideal_network P1

Use the -no_propagate option to limit the propagation of the ideal network for only the nets and pins that are electrically connected to the ideal network source. If, for example, you enter

使用 -no_propagate 选项可限制ideal network的传播，仅针对与ideal networks 的源物理连接的net和pin。例如，如果您输入

pt_shell> set_ideal_network -no_propagate net1

only the net, net1, its driver pins, and its load pins are marked as ideal. No further propagation is performed.

If you do not use the -no_propagate option with this command, PrimeTime sets the ideal property on the specified list of pins, ports, or nets and propagates this property according to the propagation rules defined in Propagating Ideal Network Properties.

如果不在此命令中使用 -no_propagate 选项，PrimeTime 将在指定的pin、port或net上设置理想属性，并根据传播Ideal networks属性中定义的传播规则传播此属性。

To remove an ideal network, use the remove_ideal_network command. To report ideal ports, pins, nets, or cells, use the report_ideal_network command, as shown in the following example:

要删除ideal networks，请使用 remove_ideal_network 命令。要报告理想的 ports、pins、nets 或 cells，请使用 report_ideal_network 命令，如以下示例所示：

pt_shell> report_ideal_network -timing -load_pin -net -cell

…

Using Ideal Latency

By default, the delay of an ideal network is zero. You can specify ideal latency on pins and ports in an ideal network by using the set_ideal_latency command. Ideal latency is accumulated along a path in the same way as a delay value.

默认情况下，ideal networks的延迟为零。您可以使用 set_ideal_latency 命令在ideal networks中的引pin和port上指定理想的延迟。理想延迟沿路径累积的方式与延迟值相同。

Note that ideal latency takes effect only if the object is ideal. If it is not in an ideal network, PrimeTime issues a warning to that effect in the report_ideal_network command.

请注意，仅当对象为 ideal 时，理想的延迟才会生效。如果不在ideal networks中，PrimeTime 会在 report_ideal_network 命令中发出警告。

Remove latency from a pin or port by using the remove_ideal_latency command.

使用 remove_ideal_latency 命令消除 pin 或port的延迟。

Using Ideal Transition

The transition time of an ideal network is zero by default. You can, however, specify an ideal transition time value with the set_ideal_transition command.

默认情况下，ideal networks的transition时间为零。但是，您可以使用 set_ideal_transition 命令指定理想的transition时间值。

If you set an ideal transition value on an object, the value is propagated from that object along the ideal network either to the network boundary pins or until another ideal transition value is encountered.

如果在对象上设置了ideal transition，则该值将沿着ideal networks从该对象传播到network boundry pins，或者直到遇到另一个理想的过渡值。

Ideal transitions you have annotated on pins or ports take effect only if the object is ideal. If the object is not ideal, PrimeTime issues a warning in the report_ideal_network command informing you of this. Use the remove_ideal_transition command to remove the transition time you set on a port or pin.

您在 pins 或 ports 上标注的理想transition仅在对象理想时生效。如果对象不理想，PrimeTime 会在 report_ideal_network 命令中发出警告，通知您这一点。使用 remove_ideal_transition 命令删除您在 port 或 pin 上设置的 transition time。

Reporting of Ideal Clocks in Full Clock Expanded Mode

By default, when you use the report_timing -path_type full_clock_expanded command, the report does not show the clock path through an ideal clock network. Instead, it shows a single line with the ideal clock latency at the clock arrival point.

默认情况下，当您使用 report_timing -path_type full_clock_expanded 命令时，报告不会显示通过理想 clock network 的 clock path。相反，它显示一行在 clock 的到达点的理想 clock latency 。

You might want to know the topological path through the ideal clock network. For example, you might want to find out which ideal clock path is reaching a register where you did not expect it.

你可能想知道通过理想 clock network 的拓扑路径。例如，你可能想找出哪个理想的 clock path 正在到达不是你期望的 register。

To report clock paths through ideal clock networks, set the following control variable:

pt_shell> set_app_var timing_report_trace_ideal_clocks true

true

pt_shell> report_timing -path_type full_clock_expanded…

With the timing_report_trace_ideal_clocks variable set to true, the report shows the full ideal clock path and potential incremental delay along the path. At the clock arrival point, the report applies an adjustment to negate the propagated delay calculation and obtain the ideal clock edge time. It then applies the ideal clock network delay.

将 timing_report_trace_ideal_clocks 变量设置为 true 后，报告将显示完整的理想 clock path 和沿 path的潜在增量 delay。在 clock 到达点，报告应用调整以否定传播的 delay 计算并获得理想的 clock edge time。然后，它应用理想的 clock network delay。

This option similarly controls reporting of paths by the report_clock_timing -verbose and report_min_pulse_width -path_type full_clock_expanded commands.

Checking the Constraints

Before you begin a full analysis, it is a good idea to check your design characteristics and constraints. Paths that are incorrectly constrained might not appear in the violation reports, possibly causing you to overlook paths with violations.

在开始全面分析之前，最好检查您的design特征和约束。约束不正确的path可能不会显示在违例报告中，这可能会导致您忽略存在违例的path。

Design Reports

Before running a full timing analysis, you can check the design with the commands in the following table. After running timing analysis, these commands can also help you to debug violations in the design.

Constraint Checking With the check_timing Command

To check for constraint problems such as undefined clocking, undefined input arrival times, and undefined output constraints, use the check_timing command. This command also provides information about potential problems related to minimum clock separation (for master-slave clocking), ignored timing exceptions, combinational feedback loops, and latch fanout. You can correct unconstrained paths by adding constraints, such as create_clock, set_input_delay, and set_output_delay.

要检查约束问题，例如未定义的 clocking、未定义的 input 到达时间和未定义的 output constraints，请使用 check_timing 命令。此命令还提供与最小 clock separation（用于 master-slave clocking）、ignored timing exceptions、组合反馈 loops 和 latch fanout相关的潜在问题的信息。您可以通过添加约束（如 create_clock、set_input_delay 和 set_output_delay）来更正不受约束的path。

The following example shows a typical check_timing report:

pt_shell> check_timing

By default, the check_timing command performs several types of constraint checking and issues a summary report like the one shown in the preceding example. To get a detailed report, use the -verbose option. To add to or subtract from the default list of checks, use the -include or -exclude option of the check_timing command or set the timing_check_defaults variable to specify the list of checks for subsequent check_timing commands. For a list of all checks performed by the check_timing command, see the man page.

默认情况下，check_timing 命令执行多种类型的约束检查，并发出如上例所示的摘要报告。要获取详细报告，请使用 -verbose 选项。要向默认检查列表添加或减去检查，请使用 check_timing 命令的 -include 或 -exclude 选项，或设置 timing_check_defaults 变量以指定后续 check_timing 命令的检查列表。有关 check_timing 命令执行的所有检查的列表，请参见手册页。

Warnings reported by the check_timing command do not necessarily indicate true design problems. To obtain more information, you can use a variety of report commands to get information about the characteristics of the design and the timing constraints that have been placed on the design.

check_timing 命令报告的Warning并不一定表示真正的设计问题。要获取更多信息，您可以使用各种 report 命令来获取有关 design 的特性和已施加在 design上的timing constraints 的信息。

Note: If timing paths are unconstrained, the check_timing command only reports the unconstrained endpoints, not the unconstrained startpoints. Similarly, for paths constrained only by set_max_delay, set_min_delay, or both rather than set_input_delay and set_output_delay, the check_timing command only reports any unconstrained endpoints, not unconstrained startpoints.

注意： 如果 timing paths 是 unconstrained 的，则 check_timing 命令仅报告不受约束的端点，而不报告不受约束的起点。同样，对于仅受 set_max_delay 和/或 set_min_delay 约束而不是 set_input_delay 和 set_output_delay 约束的路径，check_timing 命令仅报告任何不受约束的端点，而不报告不受约束的起点。

Detailed Constraint Checking and Debugging

To report incorrect constraints or other potential problems, use the detailed constraint checking and debugging capabilities of the tool. This constraint checking capability provides a broad set of predefined rules that cover problems in clocks, exceptions, cases, and design rules, such as blocked timing paths and missing clock definitions.

要报告不正确的约束或其他潜在问题，请使用该工具的详细约束检查和调试功能。这种 constraint checking 功能提供了一组广泛的预定义规则，涵盖了 clocks、exceptions、case 和 design rules 中的问题，例如 blocked timing paths 和缺失的 clock definition。

To run constraint checking from the PrimeTime shell,

• (Optional) Specify the constraint checking setup in the .synopsys_gca.setup file.
• （可选） 在 .synopsys_gca.setup 文件中指定约束检查设置。
• Specify the current design by using the current_design command. For example:
  2. 使用 current_design 命令指定当前design。例如
  pt_shell> current_design top
• (Optional) Specify a constraint checking rule file that contains user-defined violation waivers and custom rules by setting the gca_setup_file variable. For example:
  3. （可选）通过设置 gca_setup_file 变量，指定包含用户定义的违规豁免和自定义规则的约束检查规则文件。例如
  pt_shell> set_app_var gca_setup_file ./top_rules.tcl
• Perform constraint analysis by using the check_constraints command. For example:
  4. 使用 check_constraints 命令执行约束分析。例如：
  pt_shell> check_constraints
• To perform constraint analysis on another design, repeat steps 2 to 4. You can optionally specify a different rule file. For example:
  

5. 要对另一个设计执行约束分析，请重复步骤 2 到 4。您可以选择指定其他规则文件。例如：

pt_shell> current_design block

pt_shell> set_app_var gca_setup_file ./block_rules.tcl

pt_shell> check_constraints

To view the constraint checking results in the GUI, choose Constraints > View Constraint Checking Results.

要在 GUI 中查看约束检查结果，请选择 Constraints > View Constraint Checking Results。

Alternatively, you can perform constraint analysis in a separate constraint checking shell, ptc_shell. For details, see Constraint Consistency.

或者，您可以在单独的约束检查shell, ptc_shell 中执行约束分析。有关详细信息，请参阅 Constraint Consistency。