Negative Slack in Design Compiler

smc1017

I'm studying two EDA tools, and I want to know more about how to remove negative slacks.
I tried timing optimization with 'group and ungroup', and using 'compile_ultra' command.
And I understand that we can divide the DAT using the pipeline or insert a buffer to increase the DAT, but can we do this in DC?


1. What are some of the representative ways to reduce slack(Setup and hold) in the Desing Compiler and PrimeTime?
DC :
PT :


2. Can I design the pipeline and insert buffer in DC(without changing the RTL code)?


3. Can't I improve my slacks at PrimeTime?

voiluce

这是面试题目吗  ？

smc1017

voiluce 发表于 2023-2-4 20:53
这是面试题目吗  ？

No It Jyst A question

voiluce

dc focus on setup
apr handle both setup and hold

primetime use DMSA to do timing eco fix flow.