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本帖最后由 兔子IC 于 2022-2-8 21:59 编辑
Name checkPlace - Checks FIXED and PLACED cells for violations, adds violation markers to the design display area, and generates a violation report
Syntax checkPlace [<violationReportFileName>] [-clearMarker] [-honorPrerouteForFiller] [-ignoreFillerInUtil] [-ignoreOutOfCore] [-inst <list_of_instances>] [-ioPinBlockage] [-macroBlockage] [-noCheckPinAccess] [-noHardFence] [-noHalo] [-noPreplaced] [-selectedOnly]
常见用法: (1)一般我们在做完FP时,要执行一次checkPlace,看下是够有macro overlap,看是否有macro出了core区域(这个问题一定要注意,可能有时候做FP时,macro少则几十个,多则上百个,你不小心忘记摆哪个macro了,它居然还在core外,如果正好是这版你要出def去做dcg,那def就会有问题,别人插mbist也会有问题,这是常见的失误,做事情一定要认真)
(2)看初始的利用率是多少,从而预估place后利用率能达到多少,比如你们的signoff target最终是65%,那初始太低了,是不是这版try其实意义不大?当然有时候这个利用率其实并不准确,还取决于你是用DC还是DCG去做的综合,以及你的timing好坏,如果是DCG综合,那留的uncertainty比较小,没有过度优化over constraint,那place时可能cell density会增加很多,如果是DC综合则不会;其实主要还是看init和place的corr,如果好,cell uti不会变化太大,如果不好,那变化会很大。每次place之后,我们可以grep下netlist中多了多少buf,那这就是place比init多的,工具为了优化timing,fix drv之类的插的buf.总而言之,一定要对整个PR flow中每个stage的uti增加几个点,要做到心中有数,因为没有人会你更了解你的design
可以看到checkPlace能check这么多点: The checkPlace command checks for the following violations:
* Region and fence violations (Instances placed outside their region or fence)
* Out of core area violations (Instances placed partly or wholly outside the core area)
* Not placed on placement grid (Standard cells not on the placement grid, or blocks not on the manufacturing grid). If the design is using the FinFET technology, checkPlace will also check if standard cells and blocks are not aligned on the FinFET grid and report violations.
* Row orientation violations (Instances whose orientation is illegal for their row; may short power to ground)
* Tech site violations (Instances placed on tech sites not matching their cells and instances that do not have rows for their tech sites)
* Overlapping with other instance (Placed instances that overlap with other instances)
* Pin access violations (Instances with at least one signal pin that does not have routing access due to pre-wires)
* Orientation violations (Instances whose orientation is not legal based on its cell symmetry rules)
* Routing/placement blockage violations in the core area (Instances placed in an obstruction created by pre-wires or routing blockage)
The command does not check fixed macros.
* Site orientation violations (Instances whose orientation does not match the tech site orientation)
* Not of fence violations (Instances placed inside a fence to which it does not belong)
* Instance padding violations if setPlaceMode -place_detail_honor_inst_pad is set to true.
In addition to checking for violations, the command reports the following:
* Number of placed instances in the design(注意是inst数目,不是ref cell数目)
* Number of unplaced macros in the design
* Placement density, in terms of used sites over available sites
* Default power domain density
option也有很多,但是我认为你应该知道这个: -clearMarker Removes the violation markers from a previous checkPlace run, without rerunning checkPlace. 应这个option可以把产生的DRC都删掉,因为不删掉layout中会始终有白色叉,就算你修掉了DRC,这样操作不重新做checkPlace去删掉这个之前的DRC,会省点时间;其实clearDrc命令也能实现
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