SysWip — Wishbone Bus Verification IP

craybird · 发表于 2022-1-27 17:27:47

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The Wishbone Bus is an open source hardware computer bus which is used by many designs in the OpenCores project.
The Wishbone Verification IP is a solution for verification of Wishbone master and slave devices. The provided Wishbone verification package includes master and slave verification IPs and examples. It will help engineers to quickly create verification environment and test their Wishbone master and slave devices

student321 · 发表于 2022-1-27 21:33:06

kanakn

gubels · 发表于 2022-3-30 00:45:59

Good one for student tnx..

zn1884683 · 发表于 2022-4-20 11:03:32

感谢分享

juneshang · 发表于 2022-7-5 22:18:11

感谢分享

yzu_master · 发表于 2024-1-2 16:58:41

感谢分享

[资料] SysWip — Wishbone Bus Verification IP

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