Disassembly on ARM designstart simulation

lincons · 发表于 2021-9-17 14:34:39

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ARM designstart is a RTL code without gated clock, and signal names are changed into sequential number.
To disassemble the running code, the key point is to know which signal is pcwe (program counter write enable).
To find it, run a code, analyze which signal is synchronous to PC change.
M0(AT510-MN-80001-r2p0-00rel0): Ar8iu6
M3(AT421-MN-80001-r0p0-02rel0): !E4yiw6
M0 disassembly is straightforward.
M3 is more complex due to its PC+4 by pipeline.

The attached contains code to do disassembly, not contain the chip design.
You can include them in your top module.
M0:
instance testboard.uchip.umcu.ucore is logical/cortexm0_integration/verilog/CORTEXM0INTEGRATION.v
instance testboard.uchip.umcu.ucore.u_logic is logical/cortexm0_integration/verilog/cortexm0ds_logic.v
M3:
instance testboard.uchip.umcu.ucore is logical/cortexm3integration_ds_obs/verilog/CORTEXM3INTEGRATIONDS.v
instance testboard.uchip.umcu.ucore.u_logic is logical/cortexm3integration_ds_obs/verilog/cortexm3ds_logic.v
Code:
instance testboard.uchip.umcu.ucode.umem.ubeh.memory is code array, 16MB address space.