uvm 编译报错问题

zhouyunlu

ncvlog: *E,SVNOTY (../tb/tests/uart_seq_base.sv, 21|39): Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.
(`include file: (../tb/tests/uart_seq_base.sv  line 21,  file : ../tb/tests/uart_test_base.sv line 27)
`uvm_object_utils(uart_seq_base)

uart_seq_base中代码 21 行：class uart_seq_base extends uvm_sequence #(i_seq_item);

请问大佬们，这个错误可能是什么，找了很久没找到

boybeyond

可能是上一个文件缺了标点符号啥的，这个文件没有问题，那就是上一个文件的问题

A1985

In SystemVerilog syntax, if a datatype begins with an identifier,
        the identifier must refer to a type. Make sure that the typedef of the desired type
        is visible in that scope or that there are not multiple wild card import clauses
        importing typedefs of the same identifier name. The latter would make the use of
        a simple type name ambiguous; in that case, in order to disambiguate which type is
        desired you must provide a full type name of the form package_name::type_name.

anpengfei

报错是说看不见i_seq_item？？？i_seq_item在哪儿定义的？编译过了吗？

诸葛小天

一般都是include，和直接在Makefile指定路径编译造成的问题，编译时UVM组件识别不了

manyoutian

你这个问题解决没，是什么原因哦

翻滚的咸鱼

请问这个问题解决了吗？遇到同样的问题。。Syntactically this identifier appears to begin a datatype but it does not refer to a visible datatype in the current scope.

翻滚的咸鱼

诸葛小天 发表于 2020-9-1 19:42
一般都是include，和直接在Makefile指定路径编译造成的问题，编译时UVM组件识别不了 ...

那要怎么修改呢？

free2021

翻滚的咸鱼 发表于 2022-2-8 17:22
请问这个问题解决了吗？遇到同样的问题。。Syntactically this identifier appears to begin a datatype bu ...

https://bbs.eetop.cn/thread-330836-1-1.html
你看这个帖子9楼的回答

JennyLi

该文件的上一级文件中include的顺序有问题