在做混仿中遇到个问题，查过历史帖子仍无法解决，请教各位达人

枫桥夜泊2333

请教各位达人，本人新手，对linux 的许多命令也不懂，这几天查过以往的帖子，没有遇到同样的问题，第一段报的错误和很多人都一样，第二段ahdlcmi.out则不一样，看到别人的都是no such file or directory,而我的是file not recognized。我这报错的部分是verilogA DAC，目前verilogXL部分和模拟部分SpectreVerilog混仿能够出来波形，但verilogA DAC这块一直不能通过，verilogA DAC本身可以生成symbol，尝试仿真了不同的verilogA DAC，也都是遇到同样的问题，报错如下：
Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//3052_SA18219047_anaCMOS18_dac_8bit_veriloga_veriloga.va.dac_8bit.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
    ERROR (SFE-91): Error when elaborating the instance dac_8bit. Simulation should be terminated.

ahdlcmi.out文件报错如下：
/soft1/cadence/MMSIM121/tools.lnx86/cdsgcc/gcc/4.4/bin/gcc -shared -O3 -fPIC -o obj/optimize/5.0/dac_8bit_libahdlcmi.so ./obj/optimize/5.0/dac_8bit_func.o ./obj/optimize/5.0/dac_8bit_DcFuncDerLoad.o ./obj/optimize/5.0/dac_8bit_DcFuncLoad.o ./obj/optimize/5.0/dac_8bit_TranFuncDerLoad.o ./obj/optimize/5.0/dac_8bit_TranFuncLoad.o ./obj/optimize/5.0/dac_8bit_cmi_c.o  -m32 -Wl,-rpath,/usr/lib -Wl,-rpath,/lib -s
/lib/../lib/libgcc.so: file not recognized: File truncated
collect2: ld returned 1 exit status
gnumake: *** [obj/optimize/5.0/dac_8bit_libahdlcmi.so] Error 1
/soft1/cadence/MMSIM121/tools.lnx86/cdsgcc/gcc/4.4/bin/gcc -shared -O3 -fPIC -o obj/optimize/5.0/dac_8bit_libahdlcmi.so ./obj/optimize/5.0/dac_8bit_func.o ./obj/optimize/5.0/dac_8bit_DcFuncDerLoad.o ./obj/optimize/5.0/dac_8bit_DcFuncLoad.o ./obj/optimize/5.0/dac_8bit_TranFuncDerLoad.o ./obj/optimize/5.0/dac_8bit_TranFuncLoad.o ./obj/optimize/5.0/dac_8bit_cmi_c.o  -m32 -Wl,-rpath,/usr/lib -Wl,-rpath,/lib -s
/lib/../lib/libgcc.so: file not recognized: File truncated
collect2: ld returned 1 exit status

另外，用的linux系统是RedHat 5.7,virtuoso &之前环境设置如下：
$ setdt ic616
$ setdt mmsim
$ setdt ldv
$ setenv CDS_AUTO_64BITS NONE （Spectreverilog仿真报错不支持64位）
$ setenv CDS_VHDLCMI_ENABLE NO
不知道有没有人遇到过同样的问题，麻烦各位达人帮忙看看，谢谢！

phoenixson

建议放弃spectreverilog, ams不好吗

磐磬

赞同楼上，AMS功能非常强大，而且很好上手

枫桥夜泊2333

phoenixson 发表于 2019-7-1 14:06
建议放弃spectreverilog, ams不好吗

谢谢，刚开始学，参考的资料是spectreverilog,因为混仿波形已经可以仿出来，但加个verilogA总在这儿报错，所以比较着急

枫桥夜泊2333

磐磬 发表于 2019-7-1 19:36
赞同楼上，AMS功能非常强大，而且很好上手

谢谢，也正准备学AMS呢，先接触的是specterverilog