那一位用MAX PLUSII来编译仿真VERILOG？

greycat

有没有这方面的资料？最好中文版的，看HELP太慢

dragonyoo

I cannot input chinese because today OS is reinstalled and it is english version,so I use english.
In maxplusII  software,the compile and synthesis of verilog language is same as VHDL.If you are familiar with MaxplusII,it is not different between verilog and VHDL.I advice you to learn the article which has been published in the web.

dairlom

看看哈用得上不？

lumish

好像这个软件还好用吧，也比较简单。主要也就是编写程序，编译，仿真这三个步骤了。