关于tetramax的test coverage问题，第一次使用，菜鸟求助

why_how

使用tetramax测试组合电路，却发现覆盖率为0%，不知道是哪里的原因，跪求大神解答。下面附上命令行及提示：C432电路stuck faultTEST-T> source "/home/ubuntu/Test Instance/ISCAS85/CUB_v/benchmark_c432x.tcl" Warning: Current simulation model is now deleted. (M39)  Begin reading netlist ( /home/ubuntu/Test Instance/ISCAS85/CUB_v/c432x.v )...  Warning: Rule N5 (redefined module) was violated 1 times.  End parsing Verilog file /home/ubuntu/Test Instance/ISCAS85/CUB_v/c432x.v with 0 errors.   End reading netlist: #modules=0, top=c432, #lines=205, CPU_time=0.00 sec, Memory=0MB  Warning: Unused argument "-noabort". (M3)  Begin reading netlist ( /home/ubuntu/Test Instance/IWLS_benchmarks_2005_V_1.0/library/GSCLib_3.0.v )...  Warning: Rule N5 (redefined module) was violated 42 times.  End parsing Verilog file /home/ubuntu/Test Instance/IWLS_benchmarks_2005_V_1.0/library/GSCLib_3.0.v with 0 errors.   End reading netlist: #modules=0, top=c432, #lines=1421, CPU_time=0.00 sec, Memory=0MB   ------------------------------------------------------------------------------   Begin build model for topcut = c432 ...   ------------------------------------------------------------------------------   There were 0 primitives and 0 faultable pins removed during model optimizations   End build model: #primitives=43, CPU_time=0.00 sec, Memory=0MB   ------------------------------------------------------------------------------   Begin learning analyses...   End learning analyses, total learning CPU time=0.00 sec.   ------------------------------------------------------------------------------   ------------------------------------------------------------------------------   Begin scan design rules checking...   ------------------------------------------------------------------------------   Begin simulating test protocol procedures...   Test protocol simulation completed, CPU time=0.00 sec.   ------------------------------------------------------------------------------   Begin scan chain operation checking...   Scan chain operation checking completed, CPU time=0.00 sec.   ------------------------------------------------------------------------------   Begin nonscan rules checking...   Nonscan cell summary: #DFF=0  #DLAT=0  #RAM_outs=0  tla_usage_type=none   Nonscan rules checking completed, CPU time=0.00 sec.   ------------------------------------------------------------------------------   Begin DRC dependent learning...   Fast-sequential depth results: control=0(0), observe=0(0), detect=0(0), CPU time=0.00 sec   DRC dependent learning completed, CPU time=0.00 sec.   ------------------------------------------------------------------------------   DRC Summary Report   ------------------------------------------------------------------------------   No violations occurred during DRC process.   Design rules checking was successful, total CPU time=0.00 sec.   ------------------------------------------------------------------------------ TEST-T> source "/home/ubuntu/Test Instance/ISCAS85/CUB_v/test_c432x.tcl"  0 faults were removed from the fault list.   86 faults were added to fault list.   ***********************************************************   *  NOTICE:  The following DRC violations were previously  *   *  encountered. The presence of these violations is an    *   *  indicator that it is possible that the ATPG patterns   *   *  created during this process may fail in simulation.    *   *                                                         *   *  Rules:  N23                                            *   ***********************************************************   ATPG performed for stuck fault model using internal pattern source.   ----------------------------------------------------------   #patterns     #faults     #ATPG faults  test      process   stored     detect/active  red/au/abort  coverage  CPU time   ---------  -------------  ------------  --------  --------   Begin deterministic ATPG: #uncollapsed_faults=14, abort_limit=10...   0               0      0        0/14/0     0.00%      0.00          Uncollapsed Stuck Fault Summary Report   -----------------------------------------------   fault class                     code   #faults   ------------------------------  ----  ---------   Detected                         DT          0   Possibly detected                PT          0   Undetectable                     UD         72   ATPG untestable                  AU         14   Not detected                     ND          0   -----------------------------------------------   total faults                                86   test coverage                             0.00%   -----------------------------------------------              Pattern Summary Report   -----------------------------------------------   #internal patterns                           0   -----------------------------------------------  Warning: STIL patterns defaulted to serial simulation mode. (M473)  End writing file  pattern_c432x.v  with 0 patterns, File_size = 4816, CPU_time = 0.0 sec.

sijige

顶一个

linibird

楼主排排版吧，没法看啊。

guiqix

截图吧！总共才72个SA fault？

SICETN

楼主解决了吗