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小弟新手，想请教各位大神一个LVS的问题。我现在把一个标准单元库里一个单元的schematic和layout一起另存到一个地方，想在这个单元的基础上构建一个新的单元。但是我直接做LVS检查时(什么都还没改)layout里的管子都被认为是pepm或nenm，单元库里并没有这些管子，而且这些管子都被认为是一个instance了，schematic里用的enm和epm管子是库里有的，于是instance就不匹配了。我还没有改过这个单元，请问layout里的管子为什么会被认为是pepm或nenm呢？该怎样让instance匹配呢？
万分感谢！附上netlist和LVS Report。
Layout Netlist
* SPICE NETLIST
***************************************
.SUBCKT probe TERM1
.ENDS
***************************************
.SUBCKT thru TERM1 TERM2
.ENDS
***************************************
.SUBCKT v12 TERM1
.ENDS
***************************************
.SUBCKT v20 TERM1
.ENDS
***************************************
.SUBCKT v40 TERM1
.ENDS
***************************************
.SUBCKT ext TERM1
.ENDS
***************************************
.SUBCKT anmvhb G SD B
.ENDS
***************************************
.SUBCKT enmesq G D S B NW
.ENDS
***************************************
.SUBCKT schd PLUS MINUS SUBSTRATE
.ENDS
***************************************
.SUBCKT LDD G S D B
.ENDS
***************************************
.SUBCKT LDDN G S D B
.ENDS
***************************************
.SUBCKT LDDP G S D B
.ENDS
***************************************
.SUBCKT br02_b LVDD LVSS Q SUB A
** N=6 EP=5 IP=0 FDC=6
M0 LVSS A 2 SUB nenm L=6e-07 W=7.8e-06 $X=1650 $Y=2400 $D=77
M1 Q 2 LVSS SUB nenm L=6e-07 W=7.8e-06 $X=3550 $Y=2400 $D=77
M2 LVSS 2 Q SUB nenm L=6e-07 W=7.8e-06 $X=5450 $Y=2400 $D=77
M3 LVDD A 2 LVDD pepm L=6e-07 W=1.02e-05 $X=1650 $Y=16900 $D=78
M4 Q 2 LVDD LVDD pepm L=6e-07 W=1.02e-05 $X=3550 $Y=16900 $D=78
M5 LVDD 2 Q LVDD pepm L=6e-07 W=1.02e-05 $X=5450 $Y=16900 $D=78
.ENDS
***************************************
Source Netlist
************************************************************************
* auCdl Netlist:
*
* Library Name: test
* Top Cell Name: br02_b
* View Name: schematic
* Netlisted on: May 8 15:52:45 2015
************************************************************************
*.EQUATION
*.SCALE METER
*.MEGA
.PARAM
*.GLOBAL vss!
+ sub!
+ vdd!
*.PIN vss!
*+ sub!
*+ vdd!
************************************************************************
* Library Name: test
* Cell Name: br02_b
* View Name: schematic
************************************************************************
.SUBCKT br02_b A Q
*.PININFO A:I Q:O
MNMOS_1 net4 A vss! sub! enm W=7.8 L=600e-3 m=1
MNMOS_2 Q net4 vss! sub! enm W=15.6 L=600e-3 m=1
MPMOS_1 net4 A vdd! vdd! epm W=10.2 L=600e-3 m=1
MPMOS_2 Q net4 vdd! vdd! epm W=20.4 L=600e-3 m=1
.ENDS
CALIBRE LVS Report
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets.
Error: Different numbers of instances.
Error: Connectivity errors.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT br02_b br02_b
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "LVCC" "LVDD" "AVDD" "VCC" "VDD" "PS" "vdd!"
LVS GROUND NAME "LVSS" "AVSS" "ASUB" "SUB" "VSS" "GND" "NS" "gnd!" "sub!"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS YES
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES YES
LVS EXACT SUBTYPES NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE NAMES TYPES SUBTYPES VALUES
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE C PARALLEL
LVS REDUCE C(anmv) PARALLEL
LVS REDUCE C(apmv) PARALLEL
LVS REDUCE C(pipcnm) PARALLEL
LVS REDUCE C(pipcpm) PARALLEL
LVS REDUCE schd PARALLEL NO
LVS REDUCE schd SERIES PLUS MINUS NO
LVS REDUCE enmesq PARALLEL NO
LVS REDUCE enmesq SERIES S D NO
LVS REDUCE thru PARALLEL
LVS REDUCE thru SERIES TERM1 TERM2
LVS REDUCE probe PARALLEL
LVS REDUCE ext PARALLEL
LVS REDUCE v5 PARALLEL
LVS REDUCE v12 PARALLEL
LVS REDUCE v20 PARALLEL
LVS REDUCE v40 PARALLEL
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Filter
LVS FILTER D(ppnwd) OPEN
LVS FILTER D(nppwd) OPEN
LVS FILTER D(nwpsubd) OPEN
// Trace Property
TRACE PROPERTY q a a 0.1
TRACE PROPERTY c a area 0.1
TRACE PROPERTY c p peri 0.1
TRACE PROPERTY c(anmv) l l 0.1
TRACE PROPERTY c(anmv) w w 0.1
TRACE PROPERTY c(apmv) l l 0.1
TRACE PROPERTY c(apmv) w w 0.1
TRACE PROPERTY c(pipcnm) l l 0.1
TRACE PROPERTY c(pipcnm) w w 0.1
TRACE PROPERTY c(pipcpm) l l 0.1
TRACE PROPERTY c(pipcpm) w w 0.1
TRACE PROPERTY r l l 0.1
TRACE PROPERTY r w w 0.1
TRACE PROPERTY d a a 0.1
TRACE PROPERTY d p peri 0.1
TRACE PROPERTY m l l 0.1
TRACE PROPERTY m w w 0.1
TRACE PROPERTY mn l l 0.1
TRACE PROPERTY mn w w 0.1
TRACE PROPERTY mp l l 0.1
TRACE PROPERTY mp w w 0.1
TRACE PROPERTY ldd l l 0.1
TRACE PROPERTY ldd w w 0.1
TRACE PROPERTY lddn l l 0.1
TRACE PROPERTY lddn w w 0.1
TRACE PROPERTY lddp l l 0.1
TRACE PROPERTY lddp w w 0.1
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Different numbers of instances (see below).
Error: Connectivity errors.
LAYOUT CELL NAME: br02_b
SOURCE CELL NAME: br02_b
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 6 6
Instances: 0 4 * ME (4 pins)
3 0 * MN (4 pins)
3 0 * MP (4 pins)
------ ------
Total Inst: 6 4
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 5 5
Nets: 5 6 *
Instances: 0 4 * ME (4 pins)
1 0 * _invx2b (6 pins)
------ ------
Total Inst: 1 4
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net LVDD ** no similar net **
--------------------------------------------------------------------------------------------------------------
2 Net LVSS ** no similar net **
--------------------------------------------------------------------------------------------------------------
3 Net SUB ** no similar net **
--------------------------------------------------------------------------------------------------------------
4 ** no similar net ** sub!
--------------------------------------------------------------------------------------------------------------
5 ** no similar net ** net4
--------------------------------------------------------------------------------------------------------------
6 ** no similar net ** vss!
--------------------------------------------------------------------------------------------------------------
7 ** no similar net ** vdd!
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
8 (_invx2b) ** missing injected instance **
Devices:
M3(1.650,16.900) MP(pepm)
M0(1.650,2.400) MN(nenm)
M5(5.450,16.900) MP(pepm)
M2(5.450,2.400) MN(nenm)
--------------------------------------------------------------------------------------------------------------
9 ** missing instance ** MNMOS_1 ME(enm)
--------------------------------------------------------------------------------------------------------------
10 ** missing instance ** MNMOS_2 ME(enm)
--------------------------------------------------------------------------------------------------------------
11 ** missing instance ** MPMOS_1 ME(epm)
--------------------------------------------------------------------------------------------------------------
12 ** missing instance ** MPMOS_2 ME(epm)
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 2 2 3 3
Nets: 2 2 3 4
Instances: 0 0 0 2 ME(enm)
0 0 0 2 ME(epm)
0 0 1 0 _invx2b
------- ------- --------- ---------
Total Inst: 0 0 1 4
o Statistics:
4 layout mos transistors were reduced to 2.
2 mos transistors were deleted by parallel reduction.
o Layout Names That Are Missing In The Source:
Ports: LVDD LVSS SUB
Nets: LVDD LVSS SUB
o Initial Correspondence Points:
Ports: Q A
**************************************************************************************************************
UNMATCHED OBJECTS
LAYOUT SOURCE
**************************************************************************************************************
LVDD on net: LVDD ** unmatched port **
LVSS on net: LVSS ** unmatched port **
SUB on net: SUB ** unmatched port **
** unmatched net ** vdd!
** unmatched port ** vdd! on net: vdd!
** unmatched port ** sub! on net: sub!
** unmatched port ** vss! on net: vss!
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time: 0 sec
Total Elapsed Time: 0 sec |
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发表于 2015-5-9 07:26:05
