[全职] Synopsys 上海/北京 急招DDR/PCIe/VIP CAE

Domiliu

If you have any interest in the position, please send your bilingual resume as

attachments to
dmliu@synopsys.com

1\ Synopsys DDR PHY CAE

Location: Shanghai/Shenzhen

Description

As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers.

Requirements

Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design.

Domain knowledge of the DDR3/2 Protocols with relevant experience is a plus.

Recent experience with ASIC implementation EDA tools and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired.

http://search.51job.com/job/62297691,c.html

2\ Job title:  VCS/VIP CAE:

Location: Shanghai

The CAE responsibilities include onsite deployment of industry leading automation and verification technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement.

Deployed across thousands of projects, Synopsys VIP supports AMBA, PCI Express, USB, MIPI, DDR, LPDDR, HDMI, Ethernet, SATA/SAS, Fibre Channel, OCP and others. Synopsys Verification IP supports advanced SystemVerilog-based testbenches including built-in methodology support for UVM and VMM.

Requirements

Real project experiences in ASIC/SoC verification are required.

Proficient with HDL (Verilog/VHDL), HVL(e/Vera/SystemVerilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering.

Experience on VMM/OVM/UVM and knowledge of SNPS verification IPs are preferred. Knowledge and experience on protocols like MIPI, PCIE and USB will be a plus.

3\ Synopsys IP CAE (PCIe)

Location: Beijing/Shanghai

Description

CAEs work closely with customers of DesignWare IP in different applications and pushing the envelope in different ways, through various design stages from integration to Silicon debug of their chips and ultimately contribute to customers’ success using Synopsys IP. Occasional travel will be required.

Requirements

•             Candidate must be highly independent with a “can-do” attitude coupled with a strong understanding and extensive experience in overall ASIC design process is required (specific experience in synthesis, STA and DFT).

•             Domain knowledge of the PCIe protocols is a strong plus.

•             Technical background and previous experience with digital design including System/Silicon Debug experience is highly desirable.

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