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本帖最后由 fcwr_004 于 2014-2-12 16:12 编辑
JOB DESCRIPTION:
- Build system functional model based on technical specification or product description and requirement with system verilog or systemC.
- Make test plan and write testbench to verify functionality and performance of ASICS.
- Develop/maintain/enhance environment tools/scripts/make files.
QUALIFICATION:
- BSEE with minimum 2-year experience in ASIC verification.
- Good knowledge on (system verilog or systemc) and verilog.
- Hands on experience with simulation and verification tools, such as NC, Questasim/VCS.
- Proficiency in one of Specman E/Vera/SystemVerilog/SystemC verification tools.
- Strong teamwork and communication ability.
如有意向,欢迎访问IC人才网链接投递简历http://www.jobic.cn/zhaopin/job_58338.html
简历接收邮箱:mina@jobic.cn chao.zhou@montage-tech.com |
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