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公司地址位于漕河泾园区内,JD如下,待遇优厚。有意者请联系: fanny_huang@newedgetech.net
Title: Digital front end engineer
The candicate will work with the mixed signal design team on the wirelesspower product development. The tasks will include: - work with the marketing and analog design team on the product definition
- take part in the mixed signal ASIC RTL design, top level intergration and simulation
- take part in the analog circuit behavior modeling
- perform synthesis, DFT insertion, formal verification, STA, and ATPG
- work with the analog design team on the co-simulation.
Requirment Must - Experience on ASIC development from product concept define to release.
- Good knowledge in verilog RTL coding and debugging.
- Ability to build up the efficient auto-check simulation platform.
- Basic knowledge of the ASIC backend flow: synthesis, formal check, timing analysis, DFT/MBIST, power anaysis, ATPG
- Familiar with C/matlab
Preferred
- Processor/MCU/SOC design/intergration/verification experience
- mixed-signal ASIC development experience
- skills in scripts lauguage: like the cshell, tcl, perl ruby and Linux OS
- knowledge of the serial control/debug interfaces such as the I2C/SPI/UART/JTAG
knowledge of the ROM/RAM/EEPROM/FLASH/OTP/MTPintergration and mass product test |