【全职社招】AMD上海研发中心热招以下职位

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1.Title: Senior Manager of Graphics Engineering, CDC Platform Engineering

Position Summary
As part of the Platform Engineering team in AMD’s China Design Center in Shanghai, the Manager of Graphics Engineering will be responsible for developing and validating cutting-edge graphic products, while leading a multi-disciplined engineering team, including System Engineering, Board Design, Diagositics, PCB Layout and Mechanical Engineering. The Manager, while partnering with North American colleagues, will manage work assignments and coordinate results globally, be responsible for building and motivating a high performance team as well as driving continual process improvement and deepening the team’s technical capabilities.
   
Reports To: Sr Director, CDC Platform Engineering
Location:      Shanghai, China
Responsibilities
• Develop and validate graphics products; manage the entire NPI process with high-quality results and efficient delivery.
• Continue to build and develop the graphics engineering team, growing the technical capabilities in the platform design, system engineering, diagnostics, layout and mechanical design areas.
• Collaborative work with cross-function team with CDC and North-American counterparts.
• Actively participate as a CDC staff member in the direction setting, planning, and strategic discussions for CDC’s long-range plan.
Qualifications
The Sr Manager of Graphics Engineering is required to have excellent communication skills, is a team player, possesses managerial and technical skills, is a self starter, and is well organized.
• A good communicator with the interpersonal skills to deal with a wide range of individuals at all levels, within and outside the China Design Center.  Possesses the ability to listen actively.  Fosters an open communication environment. Uses communication as a strategic tool.
• A team player and leader who is highly motivated and is interested in building effective organizations.  Thrives on challenges and displays a positive ‘can-do attitude’ toward solving the task at hand.  A change agent willing to constantly push for better, more efficient and effective ways of managing his/her team.
• Possesses solid engineering management skills, and can identify both problems and opportunities to make sound recommendations to the executive team. Technical background in the platform technologies would be desirable.
• Is well organized, with a high intellectual capacity, curiosity, and innovative flare. Results oriented and takes ownership. Disciplined and data driven orientation, AND decisive. Unquestioned integrity.
• Minimum of 8 years of management and technical experience working in MNC.
• The ability to communicate effectively in both spoken and written English and Mandarin.
• BS in Electrical Engineering or equivalent is required.  An advanced engineering degree (MS or Ph.D.) would be an added plus.
2. Title: Senior /MTS Engineer of Physical Design
Job Description:  
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
1. MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC design
2. 5+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate strong leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hard working and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts
3. MTS Design Engineer – DFT
Job Description:

Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics

Requirements/Qualifications:

      -   BS in EE & CS.  MS preferred, with 4+ years experience.
-   Hands on working experience on ASIC DFT design and verification
-   Familiar with entire ASIC design flow
-   Experience with micro processor design a big plus
-   Should have strong problem solving skills
-   Good English hearing, speaking, reading and writing capabilities
-   Good communication skills
4. Title: MTS ASIC Design Verification Engineer – VIP DV
AMD’s SCBU APU Design Verification team is looking for highly motivated Verification Engineers to work on next generation APU SoC development.

KEY RESPONSIBILITIES:
- Work closely with the SoC design team on understanding the APU system features being designed;
- Develop and execute test plans for system level functional features related to Video Codec, Audio Processor, Display Port, Security, PCIe Controller;
- Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM;
- Develop and refine test libraries, model and test cases;
- Apply functional coverage/assertion into testbench as enhancement;
- Support bring-up test plan and silicon validation for video IP/solutions;

REQUIREMENTS:
- At least 5 years DV experience with good understanding on IP level verification and system level verification;
- Deep knowledge of Video coding standards such as AVC, MVC, SVC, HEVC, MPEG4-2, VP8, MPEG-2, VC1 etc is a big plus;
- Experience on Security, Memory Controller is preferred;
- Experience with current verification methodologies (UVM, OVM, VMM...)
- Experience using Perl or other UNIX scripting languages for flow automation
- Good understanding on C/C++/Perl/Shell language;
- Be fluent in English speaking and writing;
5. MTS ASIC Design Verification Engineer – VIP DV
AMD’s SCBU APU Design Verification team is looking for highly motivated Verification Engineers to work on next generation APU SoC development.

KEY RESPONSIBILITIES:
- Work closely with the SoC design team on understanding the APU system features being designed;
- Develop and execute test plans for system level functional features related to Video Codec, Audio Processor, Display Port, Security, PCIe Controller;
- Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM;
- Develop and refine test libraries, model and test cases;
- Apply functional coverage/assertion into testbench as enhancement;
- Support bring-up test plan and silicon validation for video IP/solutions;

REQUIREMENTS:
- At least 5 years DV experience with good understanding on IP level verification and system level verification;
- Deep knowledge of Video coding standards such as AVC, MVC, SVC, HEVC, MPEG4-2, VP8, MPEG-2, VC1 etc is a big plus;
- Experience on Security, Memory Controller is preferred;
- Experience with current verification methodologies (UVM, OVM, VMM...)
- Experience using Perl or other UNIX scripting languages for flow automation
- Good understanding on C/C++/Perl/Shell language;
- Be fluent in English speaking and writing;
6.ISP IP System Engineer
[Responsibility]
1. Support ISP Pre-silicon emulation
2. Extract the feature list with design teams and from internal documents;
3. Generate/maintain the detailed post silicon test plan for ISP IP enablement and optimization by cooperating with the complete cross-functional teams;
4. Generate the bring up plan with ISP bring up teams to collect, monitor and track the bring up execution status updates.  
5. ISP related issues debug/track/ close, including HW/SW issues, internal/customer issues;
6. Cooperate with ISP validation to generate the validation test plan;

[Requirement]
1. Experience with image sensor or products containing ISP;
2. Solid knowledge in optical system, imaging and image quality;
3. Good understanding of the chip design, implementation, and bring up processes;
4. Excellent communication and leadership skills among different functional teams;
5. Experience in HW, SW, and system level debugging and triage;
6. Familiar with semiconductor reliability;
7. Experience in risk assessment and mitigation methodology.
8. Fluent English both oral  and written;
Master degree
7. ISP tuning engineer
[Responsibility]
1. Image Sensor/sensor module calibration and tuning for AMD’s ISP;
2. Image quality assessment, fine tuning, and certification for AMD and AMD’s customers;
3. Calibration/tuning tool chain development and process documentation;
[Requirement]
1. Solid knowledge in optical system, imaging and image quality;
2. Strong C/C++ and Matlab programming skills;
3. Experience in mobile camera/sensor calibration/tuning process;
4. Familiar with image and color processing techniques, include 3A(AWB, AE, and AF), gamma correction, demosaicing, denoising, WDR and etc.
5. Familiar with image quality certification process is a plus;
6. Master degree
8.Sr. Sys/Test Validation Engineer
DESCRIPTION OF DUTIES:
• Response to validate the system and silicon for internal design teams.
• Analyze each ASIC block and silicon feature and develop test plans
• System load stress test with voltage, frequency and silicon process margining
• Analyze the failures found in testing and support the internal design team to find the root cause of the issues;
• Write reports on root cause of issues and provide future test plan improvements.
• Develop test script to simplify test procedures
• Develop test plan based on each individual function block Participate in developing Validation test strategy and methodology.
• Participate in defining, reviewing and improving Validation test plan/procedure.
• Communicate with various internal departments to resolve anomalies.
PREFERRED EXPERIENCE:
• Bachelor degree in software or computer engineering
• Minimum 4 years system automation and test experience.
• PC x86 architecture experience, system level knowledge of the following subsystems: Memory, PC Buses, Processor, Chipset
•  Familiar with discrete Graphic Card and x86 PC Architecture.
• Familiar with theory of HDMI, DVI, DP, LVDS, eDP, PCI Express, Crossfire, Wireless Display, etc.
• Strong knowledge on Linux operating systems (RHEL, SLES, Ubuntu, Fedora)
• Strong knowledge on Microsoft Windows operating systems (2008 Srv, 2003 Srv, Win7, Vista, XP)
• X86 software experience, configure and change BIOS settings, install and configure device drivers
• Read and understand motherboard schematics – able to locate components on the motherboard, based on the schematic info.
• Good written and oral communication skills in both English and Chinese.
• Self-motivated, able to work independently and effectively to meet time requirement.
• Teamwork - enthusiastically work with others, display team spirit, and support group decisions.
9. Title: Principle/Senior Staff Design Architect for 10GE+ IP
- Own IP architecture definition, derive functional and design specifications and analyze feasibility of technical and architectures.
- Discuss with SW architect to generate an optimized HW/SW partition of the system architecture
- Guide the design team to implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Support the Front-End Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan.
- Support FW/SW bring-up and debugging
- Working as the overall technical expert of contact on the 10GE area.
Essential Functions:
Architecture, Algorithm, RTL, Performance modeling
Essential Requirements:
- Rich Experience in 10GE+ IP solution, including HW IP and SW stack
- Deep understanding of
• 10GbE+ solutions from the industry leading companies
• basic offload engines used in 10GbE/40GbE, such as
o TCP transmit segmentation offloading
o TCP Large receive offload
o Receive side scaling
• Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
• Advanced filtering and classification: flow based and L3 protocol based
• Data-center bridging, PFC/ETS/DCBX/QCN
• Device virtualization, SR-IOV/VEB/VEPA
• Advanced offload engine
o TCP offload: TOE
o Storage offload: iSCSI HBA/FCoE HBA
o RDMA: RoCE/iWARP
o Security offload: IPSec
• PHY interfaces
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape‐out experience
- Should have strong problem solving skills

10. Senior Staff/Staff Design Lead for Wired Connection IP
- Participate IP and SoC level architecture definition, create IP architectural spec, derive functional and design specifications and analyze feasibility of technical and architectures.
- Implement design with Verilog to achieve specification goals. Simulate and debug the codes in coding stage.
- Define timing constraints and support the FE Integration team to deliver qualified netlist. Feedback to Physical Design team to help to close timing and check floorplan
- Discuss with SW team to generate an optimized HW/SW partition of the functionalities
- Support FW/SW bring-up and debugging
- Working as the technical point of contact in the Wired Connection IP area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow efficiency.

Essential Functions:
Architecture, RTL, Synthesis, STA, Timing Analysis, Constraints
Essential Requirements/Qualifications:
- Proven IP / SoC Design / Integration Experience
- Must have strong background on IP development
Desired:
- Enthusiasm on technical topics
- Major in EE & CS
- Must be proficient in Verilog coding, debugging and modeling
- Deep understanding of below technical aspects would be an asset:
10GbE+ solutions from the industry leading companies
basic offload engines used in 10GbE/40GbE, such as
TCP transmit segmentation offloading
TCP Large receive offload
Receive side scaling
Basic filtering and Classification: Unicast/multicast/broadcast, ACLs
Advanced filtering and classification: flow based and L3 protocol based
Data-center bridging, PFC/ETS/DCBX/QCN
Device virtualization, SR-IOV/VEB/VEPA
Advanced offload engine
TCP offload: TOE
Storage offload: iSCSI HBA/FCoE HBA
RDMA: RoCE/iWARP
Security offload: IPSec

- 10 gigabit+ Ethernet IP design experience would be an asset
- Ethernet HW/SW performance analysis experience would be an asset
- Be familiar with ASIC design flow, such as synthesis, DFT, timing analysis, ECO etc
- Be familiar with shell/perl/tcl programming in linux OS.
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
- Have mass production tape‐out experience

11. Member of technical staff for IC design engineering (MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.  
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface,  Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
12. Design Verification MTS for Graphics Hardware
Position Summary
In this key role, the candidate will be responsible for low power implementation and verification of hardware.

Key Relationships
Report To:  Manager of SRDC

Essential Functions:
• Development of infrastructure for verification of hardware in GFX IP.
• Develop verification environments for feature verification, and use the automated regression infrastructure setup for IP level and IP on SoC level functional verification.
• Low power design and verification for specific hardware functionality in Front-end.
• Improve the low power IP delivery for variant SoCs
Requirements/Qualifications:
• BS, MS or PhD in Electrical Engineering or Computer Science.
• 6+ years of ASIC verification or low power design experience
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Advanced programming knowledge on Verilog/SystemVerilog, C/C++
• Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
• Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
• Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically.
• Demonstrates leadership ability preferred.

Skills/Competencies:
• Good design verification experience
• Good communication
• Strong problem solving skills
• Low power design verification or computer graphics knowledge are plus

Desired:
• Team Lead experience
• Design Verification experience
13. Sr. Fro-end ASIC Design CAD engineer
Position Summary
 Participate in the design and implementation of the leading edge, front-end ASIC design flow
 Participate in the research of Design Methodology to improve automation and  productivity to produce AMD's new high-quality cutting-edge APU and GPU products
 Technical support and programming
 Interface with EDA vendors on technology
Key Relationships
Reports To: Angela Xue
Direct Reports: Angela Xue

Peer Relationships:
Other Relationships:

Essential Functions:

Essential Requirements/Qualifications:
1. Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience
2. Experience in Front-end digital design and VerilogHDL is required
3. Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow
4. Familiar with SRAM design and behaviour is a plus
5. Familiar with one or more ASIC flows (logic synthesis, STA etc.) and usage of related EDA tools is a plus
6. Good written and spoken English
7. Good communication skills and be able to work both independently and in a team

14. D3D engineer-催化剂驱动部门
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
15. Senior Software Development Engineer-Windows Graphic Base Driver
- Work as part of the global base graphics engineering team to design and maintain the graphics device driver
- Resolve problem reports related to graphics device driver including troubleshooting, debugging, & defect correction
- Specify, design, and implement new ASIC and software features
- Coordinate closely with peers at both Asia and North America to ensure timely and effective communication of all assigned work activities.
- 20%~50% travel time between China Mainland and Taiwan expected.
DESIRED EXPERIENCE:
- Experience in multi-threaded programming in a x86 architecture in both kernel & user modes.
- Object-oriented design & programming
- C/C++ programming
- Experience with software debugging and related tool such as WinDbg or gdb in an x86 architecture in both kernel & user modes is a plus
- Min. 3 years direct experience in Windows or Linux graphics driver development is preferred
- Experience in Low-level programming of hardware devices is preferred
- Experience with display technologies (DisplayPort, HDMI, Stereo 3D display, wireless display, etc.) is a plus
DESIRED KNOWLEDGE, SKILLS & CHARACTERISTICS
- In depth understanding of PC architecture
- In depth understanding of Operating System architecture
- Good software debugging logic and hands on knowledge
- Good verbal and written communication skill
- Excellent multi-tasking and prioritization skill
- Good team works
- Self motivated, strong initiative, can work under moderate to minimal supervision
EDUCATION
- BA/BS degree with strong academic background or equivalent experience (higher level degree a plus) in Computer Science, Electrical Engineering, Software Engineering. MS or PHD is a plus.

16.Linux Graphics 2d driver-software engineer
- DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Design, code, optimize and maintain AMD Linux graphics display driver
- AMD new graphics ASIC bring up under Linux
PREFERRED EXPERIENCE:
- Mater degree or above in C.S. or E.E.
- Good knowledge of C/C++ programming
- Good knowledge of Linux kernel programming
- Good knowledge of graphics is a plus
- Good written and verbal communication skills
- 3+ years experience in C/C++ programming
- 3+ years experience in Linux kernel development and debugging
- 3+ years experience in Linux device driver development and debugging
- Experience in graphics driver development is a plus
- Experience in XServer/X.Org development is a plus
- Fluent English language communication skills (including verbal/writing/reading), and CET-6 pass is a minimum
17.MTS/SMTS X86 Device Driver Development-software engineer
Job Description:

DESCRIPTION OF DUTIES:
- Provide technical leadership in the development of device driver
- Closely interact with ASIC design team in new feature definition and bring up for future product generation
- Architect, design and implement Android bus/device drivers and HALs for AMD ASICs
- Improve customer satisfaction and product quality by fixing problems
- Accountable on time delivery of deliverables
- Collaborate and interface with local and global management, development and test teams to deliver a complete product solution
- Regular communication via Audio/Video conference with teams in North America

PREFERRED EXPERIENCE:
- BS-CS/BS-EE with at least 7 years experience in Android/Linux device driver development, or 5 years experience for master degree
- Excellent and demonstrable C/C++ programming skills
- Experience with programming in C/Java interface would be an asset
- Experience with Linux kernel mode driver programming under Android/Linux environment.
- Experience with USB, SD, network, camera/ISP, A/V stream, power management, etc. driver development preferred
- Experience with PCI/PCI-E/AMBA/MIPI/I2C device driver development required
- Good understanding of embedded system and/or tablet architecture is a plus
- Strong analysis and problem solving skills required
- Proven interpersonal skill, technical leadership and teamwork required
- Must be fluent in both written and spoken English
- Experience working with multi-site teams preferred
18. MTS/SE for Camera/ISP SW Development (Android)
PREFERRED EXPERIENCE:
- BS-CS/BS-EE with at least 7 years’ experience in Android/Linux device driver development, or 5+ years’ experience for MS
- Good at ARM assembly and C/C++ language,  demonstrable C/C++ programming skills
- Experience with Android camera HAL, camera service programming.
- Experience with Android multimedia OpenMAX framework integration.
- Experience with Android kernel V4L2, camera sensor, VCM and flash driver programming.
- Experience with ISP, camera sensor tuning activity.
- Good understanding of embedded system and/or tablet architecture is a plus
- Strong analysis and problem solving skills required
- Proven interpersonal skill, technical leadership and teamwork required
- Fluent in both written and spoken English
- Experience of working with multi-site teams preferred

KEY Responsibilities:
- Architect, design and implement Linux/Android Camera/ISP solutions for AMD Platform Solutions
- Closely interact with ASIC design team in new feature definition and bring up for future product generation
- Improve customer satisfaction and product quality by solving technical problems
- Accountable on time delivery of deliverables
- Collaborate and interface with local and global management, development and test teams to deliver a complete product solution
- Regular communication via Audio/Video conference with global teams
19. Software engineer for OpenGL
DESCRIPTION OF DUTIES
- Implement OpenGL new features for new generation Graphic chips.
- Improve OpenGL benchmark performance.
- Work with key customers and vendors for implementation and issue solving.
- Interact with the Graphics Community .
Develop internal tools to improve development efficiency.
PREFERRED EXPERIENCE:
- Solid knowledge in C/C++ programming language, at least 5 years plus C/C++ language experience.
- Solid knowledge in Computer Graphics.
- Strong knowledge in Linux kernal, 1 year plus Linux development experience
- Strong knowledge in software development life cycle.
- Strong knowledge in debug tools usage.
- High quality team player as good team working spirits and easy going with team members.
- Prefer MS or higher education in CS or EE or Mathematic.