(Sr.) ASIC Design Verification Engineer shanghai

2492202119

qq: 2492202119
(Sr.) ASIC Design Verification Engineer

Position Description:
As part of the IP design team, the candidate will be responsible for the pre-silicon verification of in-house designed micro-processor which is a built-in component for next generation video codec IP, including:

·         Build up and maintain verification environment, including development of testbench and test generators for block-level and full-chip level simulation;

·         Develop and execute functional verification test plans, include writing tests, developing behavioral checkers and coverage/code monitors; Analyze coverage gaps and devise strategies to fill coverage holes;

·         Work with designers to debug failing tests and resolve bugs;

·         Help develop and maintain flows/scripts/tools for front-end design/verification;

Qualification:

·         BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

·         Self-motivated team player, with strong problem resolving skills;

·         Proficient and experienced in high-level verification methodology (VMM/UVM/OVM), Verilog-HDL, and hardware verification language (SystemC/SystemVerilog);

·         Familiar with video coding standard, and/or computer architecture/micro-architecture;

·         Hands-on experienced in CPU verification, including test plan and test bench development, test case development and test coverage assessment would be a great plus;

·         Experiences in assembly programming, and using scripting languages (Perl/Tcl/Bash/Csh) for flow automation;

·         Familiar with front-end ASIC design flow;

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