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centos 6.4安装ic610 license一直循环重启：
18:51:40 (lmgrd) cdslmd using TCP-port 35728
18:51:50 (cdslmd) EXITING DUE TO SIGNAL 37
18:51:50 ((lmgrd)) Loop info: MT:0 VD_HB:0 reset:10clients:0fd's:0
18:51:50 (lmgrd) cdslmd exited with status 37 (Communications error)
18:51:50 (lmgrd) Since this is an unknown status, license server
18:51:50 (lmgrd) manager (lmgrd) will attempt to re-start the vendor daemon.
18:51:50 (lmgrd) REStarted cdslmd (internet tcp_port 42301 pid 6363)
18:51:50 (cdslmd) FLEXnet Licensing version v10.8.0.7 build 26147
18:51:51 (cdslmd) Invalid license key (inconsistent authentication code)
18:51:51 (cdslmd) ==>FEATURE Cadence_3D_Design_Viewer cdslmd 16.0 31-dec-2025 uncounted \
01357D06E4AD VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=78 \
SIGN2="0D0D EA79 E0C1 4F48 4DCF 770A E1AE F9EF 70FB FF11 B46D \
CB35 F1D2 9A45 F4A3 05E1 EB0A CEF4 8396 87BA 7B4A BA27 CED9 \
F214 BED4 2DC6 BF6A F385 8BDA C611"
18:51:51 (cdslmd) Invalid license key (inconsistent authentication code)
18:51:51 (cdslmd) ==>FEATURE Capture cdslmd 16.0 31-dec-2025 uncounted FC5BE9761A8C \
VENDOR_STRING=Team_EFA_2006 HOSTID=ANY ck=115 SIGN2="172D DEBE \
A0EB 398F CC4A 6F83 94C4 9562 ED81 D592 F833 18A4 F5A7 009E \
EBE4 0F57 1D31 3017 21F4 CE68 9C92 4062 39AF 69FA 9B04 DEA3 \
F3BB 5CF1 2709 1BDA"
18:51:51 (cdslmd) Server started on jwl for: LayoutPlus
18:51:51 (cdslmd) Allegro_Librarian Allegro_Viewer_Plus PspiceAD
18:51:51 (cdslmd) PspiceAA Allegro_studio ConceptHDL
18:51:51 (cdslmd) PCB_librarian_expert SiP_Digital_Architect_GXL SiP_Digital_Architect_L
18:51:51 (cdslmd) SiP_Digital_Architect_XL SiP_Digital_Layout_GXL SiP_Digital_SI_XL
18:51:51 (cdslmd) SiP_RF_Architect_L SiP_RF_Architect_XL SiP_RF_Layout_GXL
18:51:51 (cdslmd) Allegro_Design_Editor_620 Allegro_PCB_SI_230 Allegro_PCB_SI_630
18:51:51 (cdslmd) SPECCTRAQuest_EE PCB_designer CHDL_DesignAccess
18:51:51 (cdslmd) PE_Librarian Checkplus_Expert Concept_HDL_rules_checker
18:51:51 (cdslmd) Concept_HDL_studio PCB_design_studio adv_package_designer_expert
18:51:51 (cdslmd) PCB_studio_variants PCB_design_expert adv_package_engineer_expert
18:51:51 (cdslmd) SPECCTRAQuest_SI_expert Concept_HDL_expert Allegro_design_expert
18:51:51 (cdslmd) advanced_package_designer Allegro_designer_suite OrCAD_PCB_Router
18:51:51 (cdslmd) OrCAD_PCB_Designer_PSpice OrCAD_PCB_Designer UNISON_SPECCTRA_6U
18:51:51 (cdslmd) SPECCTRA_Unison_Ultra SPECCTRA_Unison_PCB Unison_SPECCTRA_4U
18:51:51 (cdslmd) Allegro_PCB_Design_620 Allegro_Package_SI_620_Suite Allegro_PCB_SI_620
18:51:51 (cdslmd) Allegro_Pkg_Designer_620_Suite Allegro_PCB_Router_230 Allegro_PCB_Design_230
18:51:51 (cdslmd) Allegro_PCB_SI_630_Suite Allegro_PCB_Router_210 Allegro_PCB_Router_610
18:51:51 (cdslmd) SPECCTRA_VT SPECCTRA_QE SPECCTRA_performance
18:51:51 (cdslmd) SPECCTRA_PCB SPECCTRA_HP SPECCTRA_expert_system
18:51:51 (cdslmd) SPECCTRA_expert SPECCTRA_DFM SPECCTRA_autoroute
18:51:51 (cdslmd) SPECCTRA_APD SPECCTRA_ADV SPECCTRA_6U
18:51:51 (cdslmd) SPECCTRA_256U Allegro_performance Allegro_PCB_RF
18:51:51 (cdslmd) Allegro_PCB_Partitioning Advanced_Pkg_Engineer_3D PowerIntegrity
18:51:51 (cdslmd) SPECCTRAQuest 111 12141
18:51:51 (cdslmd) 14000 14010 14020
18:51:51 (cdslmd) 14040 14060 206
18:51:51 (cdslmd) 207 21060 21400
18:51:51 (cdslmd) 276 283 300
18:51:51 (cdslmd) 3000 3001 3011
18:51:51 (cdslmd) 302 305 311
18:51:51 (cdslmd) 3111 32100 32101
18:51:51 (cdslmd) 32120 32125 32130
18:51:51 (cdslmd) 32140 32150 32500
18:51:51 (cdslmd) 32501 32505 32510
18:51:51 (cdslmd) 32520 32521 32530
18:51:51 (cdslmd) 32760 33015 33016
18:51:51 (cdslmd) 33301 33500 33580
18:51:51 (cdslmd) 34500 34510 34511
18:51:51 (cdslmd) 34530 34570 34580
18:51:51 (cdslmd) 365 370 37100
18:51:51 (cdslmd) 374 38500 38520
18:51:51 (cdslmd) 4000 501 5100
18:51:51 (cdslmd) 550 570 681
18:51:51 (cdslmd) 70000 70110 70120
18:51:51 (cdslmd) 70130 70510 70520
18:51:51 (cdslmd) 71110 71120 71130
18:51:51 (cdslmd) 71510 71520 73510
18:51:51 (cdslmd) 73520 900 90001
18:51:51 (cdslmd) 940 945 95100
18:51:51 (cdslmd) 95115 95120 952
18:51:51 (cdslmd) 95200 95210 95220
18:51:51 (cdslmd) 95255 95300 95310
18:51:51 (cdslmd) 95320 95400 972
18:51:51 (cdslmd) 974 plotVersa LEAPFROG-CV
18:51:51 (cdslmd) _21900 Datapath_Preview_Option Virtuoso_Turbo
18:51:51 (cdslmd) Virtuoso_XL Encounter_C Virtuoso_Digital_Implement
18:51:51 (cdslmd) Virtuoso_XL_Basic Virtuoso_Schem_Option Virtuoso_Turbo_Basic
18:51:51 (cdslmd) OASIS_Simulation_Interface OASIS_RFDE Artist_Optimizer
18:51:51 (cdslmd) Artist_Statistics Corners_Analysis Affirma_3rdParty_Sim_Interface
18:51:51 (cdslmd) Affirma_RF_IC_package_modeler SpectreRF Substrate_Coupling_Analysis
18:51:51 (cdslmd) Affirma_RF_SPW_model_link Virtuoso_Core_Optimizer Virtuoso_Core_Characterizer
18:51:51 (cdslmd) ULTRASIM RELXPERT UET
18:51:51 (cdslmd) Affirma_AMS_distrib_processing ADE_VoltageStorm_Option ADE_ElectronStorm_Option
18:51:51 (cdslmd) LAS_Cell_Optimization Virtuoso_Spectre Virtuoso_Spectre_RF
18:51:51 (cdslmd) virtuoso_chip_editor Virtuoso_Layout_Migrate ConcICe_Option
18:51:51 (cdslmd) AMS_environment DRAC2CORE DRAC3CORE
18:51:51 (cdslmd) DRAC3DRC DRACDIST DRACERC
18:51:51 (cdslmd) Distributed_Dracula_Option DRAC3LVS DRACLPE
18:51:51 (cdslmd) DRACPRE DRACLVS Assura_RCX-PL
18:51:51 (cdslmd) Assura_RCX-FS Assura_RCX-MP Assura_RCX-HF
18:51:51 (cdslmd) Assura_DRC Assura_LVS Assura_MP
18:51:51 (cdslmd) Assura_OPC Assura_RCX Assura_SI-TL
18:51:51 (cdslmd) Assura_SI Assura_SiMC Assura_SiVL
18:51:51 (cdslmd) Assura_UI Assura_DV_design_rule_checker Assura_DV_parasitic_extractor
18:51:51 (cdslmd) Assura_DV_LVS_checker Physical_Verification_Sys_L Physical_Verification_Sys_XL
18:51:51 (cdslmd) skillDev Affirma_sim_analysis_env Virtuoso_Multi_mode_Simulation
18:51:51 (cdslmd) Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL Virtuoso_Schematic_Editor_GXL
18:51:51 (cdslmd) Composer_EDIF300_Connectivity Analog_Design_Environment_L Analog_Design_Environment_XL
18:51:51 (cdslmd) Analog_Design_Environment_GXL Virtuoso_Visual_Analysis_XL Composer_EDIF300_Schematic
18:51:51 (cdslmd) Virtuoso_Layout_Suite_L Virtuoso_Layout_Suite_XL Virtuoso_Layout_Suite_GXL
18:51:51 (cdslmd) Virtuoso_Constraint_API Spectre_BTAHVMOS_Models Spectre_BTASOI_Models
18:51:51 (cdslmd) tw01 tw02
18:51:51 (cdslmd)
18:51:51 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
18:51:51 (cdslmd)
18:51:51 (lmgrd) cdslmd using TCP-port 42301
哪位曾经遇到过 这种 问题 ？有什么解决办法 ？先谢谢了！ |
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发表于 2013-6-26 18:50:52
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