14-bit 2.2-MS/s Sigma–Delta ADC’s

stone1005

Abstract—This paper presents the design and test results
of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma–delta
analog-to-digital converter (ADC). The analog modulator and
digital decimator sections were implemented in a 0.35-mm
CMOS double-poly triple-level metal 3.3-V process. The design
objective for these ADC’s was to achieve 85 dB signal-to-noise
distortion ratio (SNDR) with less than 200 mW power dissipation.
Both modulators employ a cascade sigma–delta topology. The
fourth-order modulator consists of two cascaded second-order
stages which include 1-bit and 5-bit quantizers, respectively. The
sixth-order modulator has a 2-2-2 cascade structure and 1-bit
quantizer at the end of each stage. An oversampling ratio of 24
was selected to give the best SNDR and power consumption with
realizable gain-matching requirements between the analog and
digital sections.
Index Terms—Analog circuits, cascaded ADC architectures, hybrid
A/D converters, mash ADC architectures, sigma–delta modulators,
switched-capacitor circuits.

ana192712

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ccmayo

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yangruhui

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yangruhui

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audiopa

多谢！

zdahai

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lhyyym

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amirjon

thanks for sharing.........

jeffej

14-bit 2.2-MSs Sigma–Delta ADC’s