Cadence SH 招聘Sr PV Design Engineer

艾清别诺

Job description:

1.
Run place&routeflow regression weekly

2.
Analyze flow issues,such as STA issues, DRC issues or power issues, during placement, cts, routingand optimization

3.
Design real chipswith advance nodes with signoff quality. Help customer to solve flow issues.

Position requirements:

1. Ph.D or excellent MS which isfamiliar with APR flow.应届博士生或者优秀硕士生。

2. Good at STA. Know aboutplace, routing, cts, optimization and SI analysis is a plus.

3. Know about RTL synthesis

4. Good at unix scripts, cshell.Perl is a plus

5. Strong ability in analyze andsolving issues, good English skill, good team work ability.

有意向的发邮件到：xiulingl@cadence.com，谢谢

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Hi 艾清别诺,
请问下面Cadence的职位是否有在招聘？
Member of Technical Staff Hardware – T2  职位代号：5127