Cadence is looking for Principal Verification Engineer

kengteng

PrincipalVerification Engineer

Location: Shanghai/Beijing

Position description:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

Specificduties include:

--Deep understanding onASIC/SOC design flow

--Excellent knowledge of advanced verification methodologylike eRM/OVM/UVM

–Familiar with Cadence’s Incisive Plan to ClosureMethodology (IPCM)

--Proficiency in System Verilog,  System C and/or e(Specman)

–Developing and using Verification Components (eVC, OVC, UVC,VIP)
–Developing and using assertion basedverification and formal analysis methods

--Skilled in scripting language, such as Perl, C shell,Makefile
–Assessing the project verification requirements
–Operating in a lead role regardingarchitecting and implementation of project verification environment/solution.

–May coordinate/lead others within the scope of a definedproject

Essential Qualifications:

Must have BS degreewith 10+ years of applicable experience, MS degree with 7+years of applicable experience
in electricalengineering, microelectronics, comparable engineering science or solid statephysics. Essential that the individual demonstrates strong communication,verbal and written. Requires good communication skills in English.

DesirableQualifications:

Aminimum of seven years relevant experience in industry.

-Will have demonstrated hands-on experience and expertise with Cadence verification designtools or equivalent tools, flows and methodologies required to execute a verificationproject.

-Will have demonstrated successful completion of 10+ verificationprojects as an individual contributor

- Will have ARM based SoC designs at system projectverification experience

Ifyou have interest,PLS send your update CV to zhangyl@cadence.com