【上海】顶级美资公司招聘Layout

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顶级美资半导体公司，其产品广泛用于模拟信号和数字信号处理领域

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Sr. Layout Engineer
Responsibilities:
This position will participate in layout design team for analog and mixed signal circuits layout on CMOS and high voltage BCD process. Work through entire chip construction process, from preliminary floor-plan, detailed sub-block layout, and top level integration  and routing. Responsible for running full verification sequence using advanced EDA tools. The responsibilities will include but not limited to:
•            Leading top level layout  floor-plan  and integration
•            Transistor level sub-block layout based on schematics provide by designers, including careful analog considerations
•            Completion of DRC and LVS check and verification tools
•            Hold and attend layout reviews

Qualification:
•            BSEE or above
•            6+ years working experience as an analog layout design, 3+ years top-level tape out        experience, team leader background is advantage.
•            Experience of high speed circuit analog layout
•            Understand IC process basics
•            Understand circuit basics and how they impact IC layout strategy
•            Good English language skill
•            To be able to travel abroad frequently