北京-美资半导体招聘 ASIC设计和验证

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ASIC Design Engineer

The candidate must work with architecture teams to develop efficient micro-architecture for a module. In addition, the candidate needs to contribute heavily to full chip integration and flow development to minimize design effort and time.  
Primary Responsibilities:
• IP design, maintain and integration. Support physical design, board development and product engineering teams through tape-out, silicon qualification and high volume production
Qualifications:
• BS/MS EE
• 3+ years in ASIC design experience
• Experienced on SoC
• Experienced in chip level integration
• Experienced in basic aspects of ASIC flow – synthesis, timing
• Family with scripting language.
• Good written and verbal communication skills
• Ability to communicate well in English, verbal and written
• Lab/bring-up experience is a plus
• FPGA experience is a plus
• MIPS, Video, Codec and prior design experience is a plus.

Title: Senior Verification Engineer
Job Requirements:
- BSEE & 3+ years ASIC Verification experience (MSEE preferred).
- Strong Scripting language experience (i.e. Perl, Shell, Python)
- Strong verification experience with SystemVerilog, OVM, etc is a big plus.
- C / C++ & Verilog experience.
- Experience with embedded microprocessors (i.e. MIPS, ARM, SPARC, etc).
- Memory systems and Memory controller experience (i.e. DDR2, 3, etc.)
- SOC Architecture design and implementation knowledge.
- Experience on XML based database etc is also a plus.
Main Responsibilities:
- Taking charge of development & deployment of verification methodology scripting (python based).
- Developing and maintaining test plans, constrained random verification environment, etc.
- Planning & execution of system and block level verification.