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发表于 2013-12-4 15:59:32
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同志们得勤翻看sv LRM, 里面有明确的内容解决这问题:
In Verilog, the ‘define macro text can include a backslash ( \ ) at the end of a line to show continuation on
the next line.
In SystemVerilog, the macro text can also include `", `\`" and ``.
An `" overrides the usual lexical meaning of ", and indicates that the expansion should include an actual quo-
tation mark. This allows string literals to be constructed from macro arguments.
A `\`" indicates that the expansion should include the escape sequence \", e.g.
`define msg(x,y) `"x: `\`"y`\`"`"
This expands:
$display(`msg(left side,right side));
to:
$display("left side: \"right side\"");
A `` delimits lexical tokens without introducing white space, allowing identifiers to be constructed from argu-
ments, e.g.
`define foo(f) f``_suffix
This expands:
‘foo(bar)
to:
bar_suffix |
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