【上海&北京】知名美资500强诚聘IC工程师

helena_eb

SoCIntegration Engineer SoC

Responsibilities:
1.       Responsible for SoC integration anddesign of SoC-level logic including clock, reset, and DFT.
2.       Design and Verification ofAMBA-based DMA, Memory Subsystem, and all peripheral interfaces at unit leveland SoC level.
3.       Work with analog group and physicallayout team on analog macro integration and synthesis/timing analysis.
Qualifications:
1.       5 years experience on SoC designand integration.
2.       Hand-on experience in ASIC/SoC developmentfrom micro-architecture design, verification at RTL level and gate level, totiming constraint and analysis.
3.       Experience on SoC integration ofARM processor and AMBA bus for SoC.
4.       Integration of IPs includingMPEG/H264 Codec, DDR, USB, PCIe, and other IPs for SoC.
5.       Domain knowledge on Nand FlashController, USB, and PCIe is a plus.
6.       Strong DSP background is a plus

Job Title:  Sr./Staff GPU ASIC Design Engineer

City/Town:        Shanghai

Country:  China

Job Description:      

Responsibility:

a) Responsible forFront-End chip implementation including design, implementation and execution ofthe flow that starts with RTL code and ends with the delivery of a netlistpackage ready for physical design

b) Build test bench andmonitors for DUT

c) Debugfunction/performance bugs of relative memory control blocks

Requirement:

1) MS or above of EE orrelated fields.

2) A solid foundation ofComputer Architecture or DDR feature or memory controller

3) At least 3 years workexperience on Design.

4) Proficient on Verilogand asic design flow

5) Familiar with Perl orother script language

6) Fluency in English

7) Good at communication

Senior/Staff Engineer of Physical Design

City/Town:    Shanghai

Country:        China

Job Description:   DESCRIPTION OFDUTIES:

Work with global Front-End design team and physical design team forlarge scale ASIC chip physical implementation. Focus on physical design of deepsub-micron GPU chips including block level (full chip) floor planning, timingclosure, place&route, physical verification etc. The individual is expectedto be an expert in at least one PD area and provide technically leadership tothe engineering team.

Job Requirement

1. MSEE with 6+ years or Bachelor with 8+ years of industrial experiencein ASIC design

2. 3+ years or more years of experience in physical design of deepsubmicron digital ASIC chips

3. Hands on experience in large scale ASIC chip physical design

4. Knowledgeable in all aspects of deep submicron ASIC design flow

5. Successfully gone through several complete product development cycles

6. Demonstrate leadership and work well with cross-functional teams

7. Good listening, writing and speaking English

8. Good communication skills, strong interpersonal skills and theflexibility

9. Dedicated, hard working and good team player

10. Familiar with Back-End (physical design) EDA tools

11. Familiar with Front-End EDA tools is a plus

12. Familiar with Unix/Linux environment and good at scripts

除了上海之外也有location在北京的职位。感兴趣的朋友请将简历发至helena.bri@hotmail.com

或加msn聊聊～

helena_eb

顶一下～～

helena_eb

仍有效