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MentorGraphics · 发表于 2011-2-15 22:57:40

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大家都用什么验证工具?

AmoiBB · 发表于 2011-2-16 09:52:54

帮顶，也想知道

yanyanwa1021 · 发表于 2011-2-16 13:59:50

我也想知道呢

richyrichy · 发表于 2011-3-19 17:41:47

For small-sized design houses, post-sim and prime time is still the most frequently used tools to verify design after layout. Formality is too expensive for many companies. For SystemC and SystemVerilog; I don't use them up to now.

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