经典IC设计面试问题2

yanzhang98

ifference between blocking and non-blocking?(Verilog interview questions that is most commonly asked)

                                 The         Verilog language has two forms of the procedural assignment statement:         blocking and non-blocking. The two are distinguished by the = and <=         assignment operators. The blocking assignment statement (= operator)         acts much like in traditional programming languages. The whole statement         is done before control passes on to the next statement. The non-blocking         (<= operator) evaluates all the right-hand sides for the current time         unit and assigns the left-hand sides at the end of the time unit. For         example, the following Verilog program

// testing blocking and         non-blocking assignment

module blocking;
reg [0:7] A,         B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking         procedural assignment
B = A + 1;

$display("Blocking: A= %b B=         %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural         assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b",         A, B );
end
endmodule

produces the following output:         
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B=         00000100

The effect is for all the non-blocking assignments to         use the old values of the variables at the beginning of the current time         unit and to assign the registers new values at the end of the current         time unit. This reflects how register transfers occur in some hardware         systems.
blocking procedural assignment is used for combinational         logic and non-blocking procedural assignment for sequential

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