用cadence的assura跑LVS,结果电路器件和版图器件无法对应起来。工艺是smic0.18工艺文件。我感觉是binding.rul文件的有些问题,求高手指点一下,现在的binding.rul文件内容是:
c RESISTOR rndifsab
c N18 n18
c P18 p18
c N18 NPD
c N18 NPG
c P18 PL
c n33 n33
c p33 p33
c PNP18A4 pnp18
c PNP18A25 pnp18
c PNP18A100 pnp18
c PNP33A4 pnp33
c PNP33A25 pnp33
c PNP33A100 pnp33
c NPN18A4 npn18
c NPN18A25 npn18
c NPN18A100 npn18
c NPN33A4 npn33
c NPN33A25 npn33
c NPN33A100 npn33