is this a pipeline design ?

sevid

hi, everyone

if my design consists of 3 modules, of course, their I/Os have relationships.

certainly, my top design connects them together.

then,  from the system structure point of view, can i call this design (or the top module/design) a pipeline if only the outputs of each module latched ??

if not, how to design a pipeline system with verilogHDL? and if it has IF,ID and EXE levels.

pls give ur view and we'll very appreciate.

sevid

[ 本帖最后由 sevid 于 2008-11-23 23:21 编辑 ]

hpiclab

从功能处理上来说，pipeline指的是每个时钟周期都能够进行操作。举个例子，有A、B、C三个操作，如果是pipeline，那么A、B、C可以连续处理而不需要插入等待周期。

另外，不要太拘泥于形式。