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verilog 代码如下
- module reg_4(clk,num_in,num_out);
- input clk;
- input signed [4:0] num_in;
- output reg signed [4:0] num_out;
- reg signed [4:0] delay=0;
- always @(posedge clk)
- begin
- delay=num_in;
- end
- always @(negedge clk)
- begin
- num_out=delay;
- end
- endmodule
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可是综合出来不太对
- module reg_4(clk, num_in, num_out);
- input clk;
- input [4:0] num_in;
- output [4:0] num_out;
- wire clk;
- wire [4:0] num_in;
- wire [4:0] num_out;
- wire [4:0] delay;
- wire UNCONNECTED;
- assign num_out[1] = 1'b0;
- assign num_out[2] = 1'b0;
- assign num_out[3] = 1'b0;
- assign num_out[4] = 1'b0;
- DFFNSRXL \num_out_reg[0] (.RN (1'b1), .SN (1'b1), .CKN (clk), .D
- (delay[0]), .Q (num_out[0]), .QN (UNCONNECTED));
- DFFQX1 \delay_reg[0] (.CK (clk), .D (num_in[0]), .Q (delay[0]));
- endmodule
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