大佬们，VCS+Xa的数模混合仿真怎么做啊

ac1ac

最近参考网上的VCS+Xa的数模混合仿真流程，根据自己做的4位加法器电路，在addr4.v中增加了vssl,vddl，在testbench里设置了vsslh和vddl的电压，但是仿真时没有电压能输进去

                               
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ac1ac

下面是我的addr4.v和testbench
module addr4 (a, b, cin, s, cout,vddl,vssl);
input [3:0] a, b;
input cin;
output [3:0] s;
output cout;
input vddl;
input vssl;

//assign {cout, s} = a + b + cin;
endmodule
`timescale 1ns/10ps

module top;

reg [3:0] a, b;
wire [3:0] s;
reg cin;
wire cout;

task test;
input [3:0] in1, in2;
input inc;
reg [3:0] real_out, exp_out;
reg real_cout, exp_cout ;
reg vddl;
reg vssl;
begin
    vddl=1'b1;
    vssl=1'b0;
    a = in1;
    b = in2;
    cin = inc;
  #10
    real_out = s;
    real_cout = cout;
    assign {exp_cout, exp_out} = in1 + in2 + inc;
    if ($test$plusargs("COMPARE")) begin
      if (exp_out !== real_out)
        $display("COMPARE ERROR! Expected_s=%h Real_s=%h",exp_out,real_out);
      if (exp_cout !== real_cout)
        $display("COMPARE ERROR! Expected_cout=%b Real_cout=%b",exp_cout,real_cout);
    end
end
endtask

adder4 dut (.a(a[3:0]), .b(b[3:0]), .cin(cin), .s(s[3:0]), .cout(cout), .vssl(vssl), .vddl(vddl));

initial begin
$vcdpluson;
$monitor($time,,,"a= %h ",a,"b= %h ",b,"cin= %b ",cin,"s= %h ",s,"cout= %b ",cout);
#0
//test(ValueForInput1, ValueForInput2, CarryIn);
test(0,1,0);
test(0,1,1);
test(1,1,1);
test(15,15,0);
test(15,15,1);
$finish(2);
end
endmodule
AD.init设置如下，加入了加法器的网表
bus_format <%d>;
use_spice -cell adder4;
choose xa -spectre /home/rfic/TEST/input.scs -c /home/rfic/TEST/aa.cfg
d2a hiv=1.8V lov=0V node=top.dut.a<0>;
d2a hiv=1.8V lov=0V node=top.dut.a<1>;
d2a hiv=1.8V lov=0V node=top.dut.a<2>;
d2a hiv=1.8V lov=0V node=top.dut.a<3>;
d2a hiv=1.8V lov=0V node=top.dut.b<0>;
d2a hiv=1.8V lov=0V node=top.dut.b<1>;
d2a hiv=1.8V lov=0V node=top.dut.b<2>;
d2a hiv=1.8V lov=0V node=top.dut.b<3>;
d2a hiv=1.8V lov=0V node=top.dut.cin;
a2d loth=0.9V hith=0.9V node=top.dut.s<0>;
a2d loth=0.9V hith=0.9V node=top.dut.s<1>;
a2d loth=0.9V hith=0.9V node=top.dut.s<2>;
a2d loth=0.9V hith=0.9V node=top.dut.s<3>;
a2d loth=0.9V hith=0.9V node=top.dut.cout;
d2a hiv=1.8V lov=0V node=top.dut.vssl;
d2a hiv=1.8V lov=0V node=top.dut.vddl;


请问大佬们，我的这个流程是哪里出问题了呢

ac1ac

大佬们能帮忙看下吗

puxiancheng

你的spice网表是怎么来的？电压阈值是1.8V吗？

ac1ac

puxiancheng 发表于 2024-3-21 10:08
你的spice网表是怎么来的？电压阈值是1.8V吗？

大佬我用的cadence导出的input.scs，这个可以吗

ac1ac

puxiancheng 发表于 2024-3-21 10:08
你的spice网表是怎么来的？电压阈值是1.8V吗？

大佬，我在做VCS+XA仿真时总是找不到adder4.spi

***** Warning: On line "2" of mixed-signal control file "AD.init"
               subckt " adder4 " cannot be found in analog netlist.
               This command will be ignored.
Parsing design file 'testbench.v'
Parsing design file 'adder4.v'

Top Level Modules:
       top
       addr4

Error-[MSV-SETUP-IUC] Invalid use clause
AD.init, 2
"adder4"
  Module or design unit `adder4' specified in the use_spice clause in the
  Mixed Signal setup file cannot be found in the Spice library.

这是我的VD.init

bus_format <%d>;
use_spice -cell adder4;
choose xa -n adder4.spi -c aa.cfg
d2a hiv=1.8V lov=0V node=top.dut.a<0>;
d2a hiv=1.8V lov=0V node=top.dut.a<1>;
d2a hiv=1.8V lov=0V node=top.dut.a<2>;
d2a hiv=1.8V lov=0V node=top.dut.a<3>;
d2a hiv=1.8V lov=0V node=top.dut.b<0>;
d2a hiv=1.8V lov=0V node=top.dut.b<1>;
d2a hiv=1.8V lov=0V node=top.dut.b<2>;
d2a hiv=1.8V lov=0V node=top.dut.b<3>;
d2a hiv=1.8V lov=0V node=top.dut.cin;
a2d loth=0.9V hith=0.9V node=top.dut.s<0>;
a2d loth=0.9V hith=0.9V node=top.dut.s<1>;
a2d loth=0.9V hith=0.9V node=top.dut.s<2>;
a2d loth=0.9V hith=0.9V node=top.dut.s<3>;
a2d loth=0.9V hith=0.9V node=top.dut.cout;
d2a hiv=1.8V lov=0V node=top.dut.vssl;
d2a hiv=1.8V lov=0V node=top.dut.vddl;
大佬能帮忙看下吗

puxiancheng

xa -spectre /home/rfic/TEST/input.scs
你直接执行这个，看你网表有没问题。没问题的话，看网表里面是不是有adder4这个模块

ac1ac

大佬网表确实有问题，我修改后能跑起来了，但是有warnning，然后和testbenchy一起仿真的话gate还是没有连接
这个是XA里面的warning
Warning: "Option override" occurs 2 times.
For all the values given to an option, the last one has precedence:
XA.log最后的您看这个有问题吗
Engine starting time = (Thu Mar 21 15:08:51 2024 )
Engine ending time = (Thu Mar 21 15:08:51 2024 )
CPU Utilization: 1.0 (requested), 0.0 (used), 0.0%
=> TR/ENGINE SUMMARY: Time taken = 0 sec, Wall time = 0 sec
Virtual memory: 411M, Peak Virtual Memory: 411M, Physical Memory: 66M.
=> TR/ANALYSIS SUMMARY: Time taken = 0 sec, Wall time = 0 sec
Virtual memory: 411M, Peak Virtual Memory: 411M, Physical Memory: 66M.
=> TR SUMMARY: Time taken = 0 sec, Wall time = 0 sec
Virtual memory: 411M, Peak Virtual Memory: 411M, Physical Memory: 66M.
Peak Virtual Memory = 411 M
Grand Total Time = 1 sec
Total Wall Time = 1 sec
Total Wall Time Excluding License Check Out Time = 1 sec
Total number of comparison errors = 0
XA done (Thu Mar 21 15:08:51 2024 ).

ac1ac

puxiancheng 发表于 2024-3-21 13:49
xa -spectre /home/rfic/TEST/input.scs
你直接执行这个，看你网表有没问题。没问题的话，看网表里面是不是 ...

大佬在和testbench仿真时有个warning

Warning-[MXIR-W] VCS-MX build is required
  Please make sure that vlogan is from the intended build

这个会影响仿真吗

puxiancheng

ac1ac 发表于 2024-3-21 15:19
大佬网表确实有问题，我修改后能跑起来了，但是有warnning，然后和testbenchy一起仿真的话gate还是没有连接 ...

这个warning应该对功能没啥影响。