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发表于 2008-1-30 14:36:28
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before sending your gds to the foundry, you have to run DRC, and LVS,
DRC will ensure that your layout doesn't violate the minimum process rule, just like if the distance of two wires are too near, during the etching process, the machine will consider that these two wires are shorted together, then after fabout, it will be one wire.
LVS will ensure that the layout and schematic is identical
and more than that, we have to run postlayout simulation to some key blocks! |
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