hspice仿真如何输出节点的电流和va模型中的变量？

nihao_ya

1、如题，在hspice仿真网表应该用什么语句来输出网表节点的电流值，并且可以用waveview查看波形？
x1 drain gate 0 ntft
比如在这句中，我想要输出结点“drain”和“0”间的电流，应该怎么写？
2、另外就是，导入va模型后，怎样把va模型里的变量输出，不是va语句的打印，要求在sp输出文件中可以看到？



新手资产不多，还望大佬笑纳！

david_reg

1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1)  //note: PIN1 is subckt pin name defined in the subckt header

2.
Output Internal Module Variables (HSPICE only)
Verilog-A internal variables, by default, are hidden from output. However,
module variables with a description or units attribute, or both, are known as
output variables, and HSPICE provides access to their values; for example,
suppose a module for a MOS transistor with the following declaration at module
scope provides the output variable cgs:
(* desc="gate-source capacitance", units="F" *) real cgs;
The cgs module variable can be printed just like a normal parameter variable.
Syntax
Instance:internal_variable
Example
.print xva_vco:freq
This example outputs internal variable frequency value of Verilog-A instance
xva_vco.

kongc

同问

zentrop

.probe isub(*)

nihao_ya

david_reg 发表于 2021-1-14 14:32
1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)

谢谢大佬，问题解决了，已采纳！

ybzsa

david_reg 发表于 2021-1-13 20:49
1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)

您好我想请问一下这样我在波形图中看到了这个电流波形，但是他一直显示是0，与前仿的对不上，是什么原因呀

david_reg

后仿真的网表可能是flat网表, 可以检查一下isub()对应的instance在后仿真的网表中是否还存在.