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[求助] hspice仿真如何输出节点的电流和va模型中的变量? |
100资产
最佳答案1. Current: Subcircuit Pin
Syntax
ISUB(X****.****)
Example
.PROBE ISUB(X1.PIN1) //note: PIN1 is subckt pin name defined in the subckt header
2.
Output Internal Module Variables (HSPICE only)
Verilog-A internal variables, by default, are hidden from output. However,
module variables with a description or units attribute, or both, are known as
output variables, and HSPICE provides access to their ...
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