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发表于 2021-1-13 13:27:07
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本帖最后由 ll_ago 于 2021-1-13 14:01 编辑
module bit_num_1detect
(
input clk,
input rst_n,
input data_in_vld,
input [31:0] data_in,
output reg [4:0] bit_num,
output reg bit_num_vld
);
reg [31:0] data_temp;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bit_num <=5'h0;
bit_num_vld <=1'h0;
data_temp <=32'h0;
end
else if(data_in_vld) begin
bit_num <=5'h0;
bit_num_vld <=1'b0;
data_temp <=data_in;
end
else if(!data_temp[0]) begin
bit_num <=bit_num +1'b1;
bit_num_vld <=1'h0;
data_temp <=data_temp>>1;
end
else
bit_num_vld <= 1'b1;
end
endmodule
当bit_num_vld为1时,对应的bit_num 就是第一个1的bit 位。
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