一本关于三维集成电路硅通孔方面详细介绍的书 书名：Designing TSVs for 3D Integrated Circuits

Shangkui

Designing TSVs for 3D Integrated Circuits

1 Introduction ................................................................... 1
1.1 More than Moore with 3-D IC Technology ............................. 1
1.2 TSV-Based 3-D IC Design Challenges ................................. 3
1.3 Contributions ............................................................. 4
1.4 Organization of Book .................................................... 5
2 Background .................................................................... 7
2.1 TSV Types................................................................ 7
2.1.1 Regular (Square or Cylindrical) TSV ........................... 7
2.1.2 Annular TSV ..................................................... 8
2.1.3 Tapered TSV ..................................................... 9
2.1.4 Coaxial TSV ..................................................... 9
2.2 TSV Integration .......................................................... 10
2.3 TSV Fabrication.......................................................... 10
2.3.1 Via First .......................................................... 11
2.3.2 Via Middle ....................................................... 12
2.3.3 Via Last........................................................... 12
2.4 Electrical Modeling of TSVs ............................................ 13
2.5 Summary ................................................................. 14
3 Analysis and Mitigation of TSV-Induced Substrate Noise ............... 15
3.1 Problem: TSV-Induced Noise ........................................... 15
3.2 Evaluation Framework for TSV-Induced Noise ........................ 18
3.3 TSV-Induced Substrate Noise Analysis ................................. 20
3.3.1 Thicker Dielectric Liner ......................................... 20
3.3.2 Backside Ground Plane.......................................... 21
3.3.3 GND Plugs ....................................................... 21
3.3.4 Comparison of Three Noise Mitigation Techniques ........... 24
3.4 Summary ................................................................. 25
4 TSVs for Power Delivery ..................................................... 27
4.1 Problem: Power Delivery for 3-D ICs................................... 28
x Contents
4.2 Design Setup ............................................................. 29
4.2.1 3-D Stacked Architecture........................................ 29
4.2.2 Power Delivery Network (PDN) ................................ 30
4.2.3 Trace Selection................................................... 31
4.3 Optimal TSV Size for 3-D PDN......................................... 32
4.4 Best TSV Granularity .................................................... 33
4.4.1 Baseline 3-D Configuration (3-D NOR) ........................ 33
4.4.2 Effects of TSV Granularity (Spacing) .......................... 34
4.4.3 Effects of C4 Granularity (Spacing) ............................ 36
4.5 Effect of Dedicated Power Delivery..................................... 37
4.6 Power Delivery Using Coaxial TSV .................................... 38
4.6.1 Reducing Blockages ............................................. 38
4.6.2 Increasing Decap................................................. 38
4.6.3 Overlaying Signal and Power Routing.......................... 39
4.7 Best Practices for 3-D PDN Design and Optimization ................. 40
4.8 Summary ................................................................. 41
5 Early Estimation of TSV Area for Power Delivery in 3-D ICs ........... 43
5.1 Related Work ............................................................. 43
5.2 Problem: Power TSV Area .............................................. 44
5.3 Power TSV Minimization Algorithms .................................. 46
5.3.1 Reduce Maximum Slack (RMS) ................................ 46
5.3.2 Reduce Somewhat Arbitrary Slack (RSAS) .................... 48
5.3.3 Reduce Slack Locally (RSL) .................................... 48
5.3.4 Improve Worst Violation (IWV) ................................ 48
5.4 Results and Discussion .................................................. 49
5.5 Summary ................................................................. 51
6 Carbon Nanotubes for Advancing TSV Technology ...................... 53
6.1 Carbon Nanotubes (CNTs) .............................................. 53
6.2 Design Setup ............................................................. 54
6.3 Substrate Area Dedicated to TSV for Power Delivery ................. 57
6.4 IR Analysis ............................................................... 58
6.5 Ldi/dt Analysis ........................................................... 59
6.6 Summary ................................................................. 62
7 Conclusions and Future Directions ......................................... 63
7.1 Summary ................................................................. 63
7.2 Future Research Directions .............................................. 64
References.......................................................................... 67
Biography .......................................................................... 75  

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