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本帖最后由 春日的白玫瑰 于 2020-2-18 16:58 编辑
岗位描述: * Work with Architecture and Software teamsto ensure micro-architecture and design is fully verified/validated acrossmultiple platforms * Contribute significantly to verificationinfrastructure development * Development of System verilog/UVM basedprotocol/traffic generators/checkers, development of test plan based onfunctional requirements
岗位要求: Masters degree desired, Bachelor's degreein CS/EE is required. 5+ years of relevant experience in asic verificationfield. * Should have worked on developing/implementingtest plans at the chip-level for complex ASICs. * Fluent in System Verilog and scriptinglanguages such as Python or Perl. * Must have intimate knowledge of UVMmethodology. * Experience in the verification of SoC andother IPs such as cpu Subsystem, Ethernet, PCIE, DDR, Serdes etc. * Knowledgeable about assertions andfunctional coverage * Experience with code coverage, formalverification tools; familiarity with evolving verification methodologies. * Very good communication skills andability and desire to work in a geographically diverse team environment. * Will be responsible for definition,development and execution of self-checking tests for complex digital ASICs
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