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发表于 2019-7-23 17:25:52
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It should be noted that set clock transition is to be used only during pre-layout
stage, before clock tree synthesis has been done. This command should never
be used for any post-layout timing analysis , after the clock tree has been
synthesized.
It should be understood that the transition value specifi ed by this command is the
time taken to transition from one state to another. However, the threshold itself for
measurement of the transition time is a property of the characterization library.
ref: Constraining Designs for Synthesis and Timing Analysis |
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