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Session 12 – Nyquist A/D Converters
Oak Ballroom, Tuesday Morning, September 18
Chair: George La Rue
Co-Chair : Yusuf Haque
The first four papers present pipelined A/D converters with resolution of 10 to 14 bits and conversion rates below 210 MS/s. These are followed by higher conversion rate circuits up to 4 GS/s.
8:25 am
Introduction
12.1 - 8:30 am
A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration
H.-Y. Lee, T.-H. Oh, H.-J. Park, J.-W. Kim, Samsung Electronics, H.-S. Lee, M. Spaeth, Massachusetts Institute of Technology
12.2 - 8:55 am
A 1.8V 10b 210MS/s CMOS Pipelined ADC Featuring 86dB SFDR without Calibration
J. Li, R. Leboeuf, M. Courcy and G. Manganaro, National Semiconductor Corporation
12.3 - 9:20 am
Low-Power and High-Speed Pipelined ADC Using Time-Aligned CDS Technique
Y.-J. Kook, U.-K. Moon, Oregon State University and J. Li, B. Lee National Semiconductor
12.4 - 9:45 am
A 1V 10b 30MSPS Switched-RC Pipelined ADC
G.-C. Ahn, M.G. Kim, P. Hanumolu and U.-K. Moon, Oregon State University
10:10 am - BREAK
12.5 - 10:25 am
A Time-Interleaved Track & Hold in 0.13µm CMOS sub-sampling a 4 GHz Signal with 43dB SNDR
S. Louwsma, E. van Tuijl, B. Nauta, University of Twente, and M. Vertregt, NXP Semiconductor
12.6 - 10:50 am
A 43mW Single-Channel 4GS/s 4-Bit Flash ADC in 0.18µm CMOS
S. Sheikhaei, S. Mirabbasi and A. Ivanov, University of British Columbia
12.7 - 11:15 am
A 57dB SFDR Digitally Calibrated 500MS/s Folding ADC in 0.18µm Digital CMOS
I. Bogue and M. Flynn, University of Michigan
12.8 - 11:40 am
A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems
A. Haftbaradaran and K. W. Martin, University of Toronto |
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cicc12.rar
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发表于 2007-9-22 05:39:41
