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岗位职责 1. Specification define 2. RTL/Gate-level implementation 3. Analysis and optimization for performance 4. Analysis and optimization for power 5. Analysis and optimization for timing 6. Design flow: lint/synthesis/sta/formal check 7. Silicon debugging
任职条件 1. MS with 5+ or 3+ years of experience in asic design 2. Experience with all phases of frontend architecture, design and validation 3. RTL Coding, design reviews, SYN, CDC, FEV 4. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug 5. Excellent knowledge of verilog and popular EDA simulation & implementation tools
6. Good experience in scripting languages like Perl, Unix shell or similar languages。
[size=13.3333px]KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
[size=13.3333px]If you interested in the job, pls sent your cv to: hr@kthr.com, thanks! [size=13.3333px]“凯轶—KT咨询”微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“凯轶—KT咨询”即可添加,欢迎大家关注!
[size=13.3333px]或者直接扫我哦!
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